CY23FS08-04 Cypress Semiconductor Corporation., CY23FS08-04 Datasheet - Page 3

• Manufacturer Part Number: CY23FS08-04
• Description: Failsafe 1.8v Zero Delay Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Table 2. Configuration Table
FailSafe Function
The CY23FS08-04 is targeted at clock distribution applications
that can or currently require continued operation, if the main
reference clock fail. Existing approaches to this requirement
have used multiple reference clocks with either internal or
external methods for switching between references. The
problem with this technique is that it leads to interruptions (or
glitches) when transitioning from one reference to another. This
often requires complex external circuitry or software to maintain
system stability. The technique implemented in this design
completely eliminates any switching of references to the PLL that
greatly simplifies the system design.
The CY23FS08-04 PLL is driven by the crystal oscillator that is
phase aligned to an external reference clock. It is aligned in a
way that the output of the device is effectively phase aligned to
reference via the external feedback loop. This is accomplished
Document Number: 001-17042 Rev. **
S[4:1]
0000
0001
0010
0100
0101
0011
0110
0111
1xxx
15.36
15.36
15.36
15.36
15.36
15.36
15.36
15.36
Min
XTAL (MHz)
-
16.384
16.384
16.384
16.384
16.384
16.384
16.384
16.384
Feedback(Internal)
Max
=CLKOUT * 1/32
-
FAIL#/SAFE
3.84
3.84
3.84
3.84
3.84
3.84
3.84
3.84
Min
Figure 2. Fail#/safe timing for input reference failing catastrophically
REF(MHz)
-
REF
4.096
4.096
4.096
4.096
4.096
4.096
4.096
4.096
Max
Missing REF
Detected
-
t
FSL
Xtal/REF
Ratio
Figure 3. Fail#/safe Timing formula
4
4
4
4
4
4
4
4
-
t
t
FSL(max)
FSH(min)
Keeping Frequency for all
CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4
Off
Off
Off
Off
Off
32
8
8
1
CLKOUTs
= t
= t
REF
REF
Off
Off
Off
Off
Off
32
8
8
1
by using a digitally controlled capacitor array to pull the crystal
frequency over an approximate range of ±100 ppm from its
nominal frequency.
In this mode, if the reference frequency fails (that is, stop or
disappear), the DCXO maintains its last setting. Then a flag
signal (FAIL#/SAFE) is set to indicate failure of the reference
clock.
The CY23FS08-04 provides four select bits, S1 through S4 to
control the reference to crystal frequency ratio. The DCXO is
internally tuned to the phase and frequency of the external
reference only when the reference frequency divided by this ratio
is within the DCXO capture range. If the frequency is out of
range, a flag is set on the FAIL#/SAFE pin notifying the system
that the selected reference is not valid. If the reference moves in
range, then the flag is cleared indicating the system that the
selected reference is valid.
+
+
Valid REF but not
Phase Aligned
25ns
25ns
Off
Off
Off
32
32
16
16
10
8
Trying to align phase between
OUT/REF Ratio
REF and Feedback
Off
Off
Off
32
32
16
16
10
8
Off
Off
32
32
32
32
32
16
20
Phase Aligned
Off
Off
32
32
32
32
32
16
20
t
FSH
CY23FS08-04
Off
32
32
32
32
32
32
16
20
Page 3 of 11
Off
32
32
32
32
32
32
16
20
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