CY23FS08-04 Cypress Semiconductor Corporation., CY23FS08-04 Datasheet - Page 2

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CY23FS08-04

Manufacturer Part Number
CY23FS08-04
Description
Failsafe 1.8v Zero Delay Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Document Number: 001-17042 Rev. **
Pinouts
Table 1. Pin Definition - 28 Pin SSOP
1,2
4,5,10,11
25,24,19,18
27
23,6,7,22
14
15
16
13
8,12
3,9
17,21
20,26
28
Notes
1. Weak pull downs on all outputs.
2. Weak pull ups on these inputs.
3. Weak pull downs on these inputs.
Pin Number
REF1,REF2
CLKB[1:4]
CLKA[1:4]
FBK
S[1:4]
XIN
XOUT
FAIL#/SAFE
VDDC
VDDB
VSSB
VDDA
VSSA
REFSEL
Pin Name
5V Tolerant. Reference clock inputs
Bank B Clock Outputs.
shown in
Bank A Clock Outputs.
No Connect, Internal Feedback.
Frequency Select Pins.
Reference Crystal Input.
Reference Crystal Output.
Valid Reference Indicator. A high level indicates a valid reference input.
3.3V Power Supply for the Internal Circuitry.
1.8V Power Supply for Bank B Outputs.
Ground.
1.8V Power Supply for Bank A Outputs.
Ground.
Reference Select. Selects the active reference clock from either REF1 or REF2.
REFSEL = 1, REF1 is selected, REFSEL = 0, REF2 is selected.
Figure 1. Pin Diagram - 28 Pin SSOP
Figure 8
CLKB1
CLKB2
CLKB3
CLKB4
VDDB
VDDC
VDDB
VSSB
VSSB
REF1
REF2
XIN
S3
S2
on page 6. CLKB3 is negtive output, CLKB4 is positive output.
10
11
12
13
14
9
1
2
3
4
5
6
7
8
28-pin SSOP
[1]
[1]
[2]
CLKB3 and CLKB4 are differential signals when terminated as
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLKA2
S1
FAIL#/SAFE
XOUT
REFSEL
FBK
VSSA
CLKA1
S4
VDDA
VSSA
CLKA3
CLKA4
VDDA
[3]
Description
.
[3]
CY23FS08-04
Page 2 of 11
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