CY29351 Cypress Semiconductor Corporation., CY29351 Datasheet - Page 3

• Manufacturer Part Number: CY29351
• Description: 2.5v Or 3.3v, 200 Mhz, 9-output Zero Delay
• Manufacturer: Cypress Semiconductor Corporation.

Table 2. Frequency Table
Table 3. Function Table
Absolute Maximum Conditions
Document Number: 38-07475 Rev. *B
Parameter
REF_SEL
Feedback Output Divider
PLL_EN
Control
ESD
V
SELA
SELB
SELC
SELD
V
V
R
Ø
Ø
V
OE#
V
FIT
LU
T
T
OUT
T
DD
DD
TT
PS
IN
JC
JA
A
S
J
H
÷2
÷4
÷8
DC supply voltage
DC operating voltage
DC input voltage
DC output voltage
Output termination voltage
Latch-up immunity
Power supply ripple
Temperature, storage
Temperature, operating ambient
Temperature, junction
Dissipation, junction to case
Dissipation, junction to ambient
ESD protection (human body model)
Failure in time
Default
0
1
0
0
0
0
0
PCLK
Bypass mode, PLL disabled. The input clock
connects to the output dividers
Outputs enabled
Description
÷ 2 (bank A)
÷ 4 (bank B)
÷ 4 (bank C)
÷ 4 (bank D)
Input Clock * 2
Input Clock * 4
Input Clock * 8
VCO
PRELIMINARY
0
Functional
Relative to V
Relative to V
Functional
Ripple frequency < 100 kHz
Non Functional
Functional
Functional
Functional
Functional
Manufacturing test
100 MHz to 200 MHz
50 MHz to 125 MHz
25 MHz to 62.5 MHz
Input Frequency Range
Condition
SS
SS
(AVDD = 3.3V)
TCLK
PLL enabled. The VCO output connects to the output
dividers
Outputs disabled (three-state), VCO running at its
minimum frequency
÷ 4 (bank A)
÷ 8 (bank B)
÷ 8 (bank C)
÷ 8 (bank D)
2.375
2000
–0.3
–0.3
–0.3
Min
–65
–40
200
–
–
–
100 MHz to 190 MHz
50 MHz to 95 MHz
25 MHz to 47.5 MHz
Input Frequency Range
105
42
10
1
V
V
(AVDD = 2.5V)
V
DD
DD
3.465
+150
+150
DD
Max
150
+85
5.5
–
–
+ 0.3
+ 0.3
÷ 2
CY29351
Page 3 of 10
mVp-p
°C/W
°C/W
Volts
Unit
ppm
mA
°C
°C
°C
V
V
V
V
V
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