CY29351 Cypress Semiconductor Corporation., CY29351 Datasheet - Page 2

• Manufacturer Part Number: CY29351
• Description: 2.5v Or 3.3v, 200 Mhz, 9-output Zero Delay
• Manufacturer: Cypress Semiconductor Corporation.

Document Number: 38-07475 Rev. *B
Pinouts
Table 1. Pin Definitions - 32 Pin TQFP Package
Notes
8
9
30
28
26
22, 24
12, 14, 16, 18, 20 QD(4:0)
2
10
31
32
3, 4, 5, 6
27
23
15, 19
1
11
7
13, 17, 21, 25, 29 VSS
1. PU = Internal pull up, PD = Internal pull down.
2. A 0.1-μF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, the
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD power supply pins.
4. V
5. Driving one 50Ω parallel terminated transmission line to a termination voltage of V
6. Inputs have pull up or pull down resistors that affect the input current.
high-frequency filtering characteristics are cancelled by the lead inductance of the traces.
is within the V
lines.
CMR
Pin
(DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the V
[1]
PP
(DC) specification.
PECL_CLK
PECL_CLK# I, PU/PD
TCLK
QA
QB
QC(1,0)
FB_IN
OE#
PLL_EN
REF_SEL
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
VDD
AVSS
Name
Supply
Supply
Supply
Supply
Supply
Supply
Supply
I, PU
I, PD
I, PD
I, PD
I, PU
I, PD
I, PD
IO
O
O
O
O
Figure 1. Pin Diagram - 32 Pin TQFP Package
PEC L_C LK
LVCMOS LVCMOS/LVTTL reference clock input
LVCMOS Clock output bank A
LVCMOS Clock output bank B
LVCMOS Clock output bank C
LVCMOS Clock output bank D
LVCMOS Feedback clock input. Connect to an output for normal operation. This
LVCMOS Output enable/disable input
LVCMOS PLL enable/disable input
LVCMOS Reference select input
LVCMOS Frequency select input, bank (A:D)
LVPECL LVPECL reference clock input
LVPECL LVPECL reference clock input. Weak pull up to VDD/2.
Ground
Ground
A VD D
F B _IN
AVSS
Type
SE LA
SE LB
SELC
SELD
VDD
VDD
VDD
VDD
VDD
PRELIMINARY
1
2
3
4
5
6
7
8
input should be at the same voltage rail as input reference clock
2.5V or 3.3V power supply for bank B output clock
2.5V or 3.3V power supply for bank C output clocks
2.5V or 3.3V power supply for bank D output clocks
2.5V or 3.3V power supply for PLL
2.5V or 3.3V power supply for core, inputs, and bank A output clock
Analog ground
Common ground
C Y29351
TT
. Alternatively, each output drives up to two 50 Ω series terminated transmission
24
23
22
21
20
19
18
17
Q C 0
VD D Q C
Q C 1
VSS
Q D 0
VD D Q D
Q D 1
VSS
Description
[5,6]
CMR
[2,3]
[2,3]
[2,3]
range and the input swing
CY29351
Page 2 of 10
[2,3]
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