RF31 Hope Microelectronics co., Ltd, RF31 Datasheet - Page 69

• Manufacturer Part Number: RF31
• Description: Rf31 Ism Receiver
• Manufacturer: Hope Microelectronics co., Ltd

6:5
6:5
Bit
Bit
7
4
3
2
1
0
7
4
3
2
1
0
Table 29. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts?
Tel: [phone]
Reserved
Reserved
Reserved
Reserved
icrcerror
icrcerror
irxffafull
irxffafull
ipkvalid
ipkvalid
Status
Status
Name
Name
ifferr
ifferr
iext
iext
Table 28. Interrupt or Status 1 Bit Set/Clear Description
Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset.
Reserved.
Set when the number of bytes in the RX FIFO is greater than the Almost Full threshold.
Cleared when the number of bytes in the RX FIFO is below the Almost Full threshold.
External interrupt source.
Reserved.
Set up the successful reception of a packet (no RX abort). Cleared upon
receiving and acknowledging the Sync Word for the next packet.
Set if the CRC computed from the RX packet differs from the CRC in the TX
packet. Cleared at the start of reception for the next packet.
Set if there is a FIFO Overflow or Underflow. It is cleared only by applying FIFO
reset to the specific FIFO that caused the condition.
Reserved.
Will be set when the number of bytes received (and not yet read-out) in RX
FIFO is greater than the Almost Full threshold set by SPI. It is automatically
cleared when we read enough data from RX FIFO so that the number of data
bytes not yet read is below the Almost Full threshold.
External interrupt source
Reserved.
Goes high once a packet is fully received (no RX abort). It is automatically
cleaned once we receive and acknowledge the Sync Word for the next packet.
Goes High once the CRC computed during RX differs from the CRC sent in the
packet by the TX. It is cleaned once we start receiving new data in the next
packet.
Fax: [phone]
E-mail: [e-mail]
Set/Clear Conditions
Set/Clear Conditions
http://www.hoperf.com
R F 3 1
69