LMX2353 National Semiconductor Corporation, LMX2353 Datasheet - Page 17

• Manufacturer Part Number: LMX2353
• Description: Pllatinum? Fractional N Single 2.5 Ghz Low Power Frequency Synthesizer
• Manufacturer: National Semiconductor Corporation

2.0 Programming Description
(Continued)
The low gain or steadystate mode for fastlocking is defined to be whenever the charge pump current selected is less than 900
µA. The high gain or acquisition mode is defined to be whenever the charge pump current is greater or equal to 900 µA. (The logic
setting of the CP_8X bit determines which of the two gain modes the user is in.) During the acquisition phase when the CP_8X
bit is set to a HIGH state, the OUT0 output becomes active LOW thereby altering the loop’s damping resistance.
The acquisition phase is terminated by setting the CP_8X bit LOW resulting in the OUT0 output being OFF or TRI-STATE. When
in fastlock mode, the OUT_0 and OUT_1 bits are don’t care bits, and the OUT1 output is at TRI-STATE.
TEST MODE: The OUT0/OUT1 test mode occurs when the TEST bit (F2_17) is set HIGH. This mode is intended for NSC
production test only. Selecting this mode overrides the Fastlock
™
and GEN PURPOSE modes.
2.5.4 Serial Data Input Timing
DS101124-8
Notes: Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V
/2. The test waveform has an edge rate of 0.6 V/ns with
cc
amplitudes of 2.2V
@
V
= 2.7V and 2.6V V
= 5.5V.
CC
CC
17
www.national.com