LMX2353 National Semiconductor Corporation, LMX2353 Datasheet - Page 14

• Manufacturer Part Number: LMX2353
• Description: Pllatinum? Fractional N Single 2.5 Ghz Low Power Frequency Synthesizer
• Manufacturer: National Semiconductor Corporation

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Most Significant Bit
_21
23
F1
0
2.0 Programming Description
R:
P:
2.4 F1 REGISTER
If the ADDRESS[1:0] field is set to 0 0, data is transferred from the 24-bit shift register into the F1 register when Latch Enable (LE)
signal goes high . The F1 register sets the fractional divider denominator FRAC_16 bit and F
The rest of the bits F1_0 - F1_16, and F1_21 are Don’t Care.
Note:0 denotes setting the bit to zero.
2.4.1 FRAC_16
The FRAC_16 bit is used to set the fractional compensation at either 1/16 or 1/15 resolution. When FRAC_16 bit is set to one,
the fractional modulus is set to 1/16 resolution, and FRAC_16 = 0 corresponds to 1/15. See section 2.3.5 for fractional divider
values.
2.4.2 F
The F
detect output is provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is
selected, the pin is HIGH, with narrow pulses LOW. See typical Lock detect timing in section 2.4.2.4.
2.4.2.1 F
Reserved - Denotes a disallowed programming condition.
2.4.2.2 Lock Detect (LD) Digital Filter
The LD Digital Filter compares the difference between the phase of the inputs of the phase detector to a RC generated delay of
approximately 15 ns. To enter the locked state (Lock = HIGH) the phase error must be less than the 15 ns RC delay for 5
consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approximately 30 ns. To exit the locked
state (Lock = LOW), the phase error must become greater than the 30 ns RC delay. If the PLL is unlocked, the lock detect output
will be forced LOW. A flow chart of the digital filter is shown next.
FRAC
_16
_20
F1
22
o
LD word is used to set the function of the Lock Detect output pin according to the Table 2.4.2.1 below. Open drain lock
O
FRAC_16
Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
Preset modulus of dual modulus prescaler (P = 16 or 32)
LD
O
LD Programming Truth Table
F1_19
Bit
_19
21
F1
0
0
0
0
1
1
1
1
F
_18
O
F1
20
LD
_17
F1
19
_16
F1
18
Location
_15
17
F1
F1_20
F1_18
_14
16
F1
0
0
1
1
0
0
1
1
_13
15
F1
Data Field
(Continued)
_12
14
F1
SHIFT REGISTER BIT LOCATION
These bits should be set to zero
_11
13
F1
Fractional Modulus
14
_10
F1
12
Function
F1_17
11 10
F1
_9
0
1
0
1
0
1
0
1
F1
_8
F1
_7
9
F1
_6
8
F1
_5
7
out
F1
_4
6
/ Lock Dectect output F
1/15
0
F1
_3
F
Analog Lock Detect
5
Digital Lock Detect
o
N Divider Output
R Divider Output
LD Output State
(Open Drain)
F1
_2
4
Reserved
Reserved
Reserved
Reserved
F1
_1
3
Least Significant Bit
F1
_0
2
1/16
Address Field
O
1
1
0
LD word.
0
0