LMX2353 National Semiconductor Corporation, LMX2353 Datasheet - Page 12

• Manufacturer Part Number: LMX2353
• Description: Pllatinum? Fractional N Single 2.5 Ghz Low Power Frequency Synthesizer
• Manufacturer: National Semiconductor Corporation

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Most Significant Bit
CTL_WORD[2:0]
_21
23
N
2.0 Programming Description
2.2.4.2 Phase Detector Polarity (PD_POL)
Depending upon VCO characteristics, the PD_POL (R_15) bit should be set accordingly:
When VCO characteristics are positive like (1), PD_POL should be set HIGH;
When VCO characteristics are negative like (2), PD_POL should be set LOW.
2.3 N REGISTER
If the ADDRESS[1:0] field is set to 1 1, data is transferred from the 24-bit shift register into the N register which sets the PLL’ s
19-bit N-counter, prescaler value, counter reset, and power-down bit. The 19-bit N counter consists of a 4-bit fractional numerator,
FRAC_CNTR[3:0], a 5-bit swallow counter, A_CNTR[4:0], and a 10-bit programmable counter, B_CNTR[9:0]. Serial data format
is show below. The divide ratio (NB_CNTR) must be
2.3.1 CTL_WORD (N_19 -N_21)
2.3.2 Control Word Truth Table
2.3.2.1 Counter Reset (CNT_RST)
The Counter Reset enable bit when activated allows the reset of both N and R counters. Upon removal of the reset bit, the N
counter resumes counting in “close” alignment with the R counter (the maximum error is one prescaler cycle).
2.3.2.2 Power Down (PWDN)
Activation of the PLL PWDN bit results in the disabling of the N counter divider and de-biasing of the f
state). The R counter functionality also becomes disabled when the power down bit is activated. The OSC
impedance state as well during power down. Power down forces the charge pump and phase comparator logic to a TRI-STATE
condition. The MICROWIRE control register remains active and capable of loading and latching in data during all of the power
down modes.
2.3.2.3 Prescaler Modulus Select (PRESC_SEL)
The PRESC_SEL bit is used to set the RF prescaler modulus value. The LMX2353 is capable of operating from 500 MHz to
1.2 GHz with the 16/17 prescaler, and 1.2 GHz to 2.5 GHz with the 32/33 prescaler selection.
PWDN_MODE
PRESC_SEL
_20
22
CNT_RST
N
PWDN
Bit
_19
21
N
CNT_RST
_18
20
N_21
N
_17
19
N
Location
F2_19
N_19
N_20
N_21
_16
18
N
_15
17
N
NB_CNTR[9:0]
_14
16
N
Power Down Mode Select
Prescaler Modulus Select
_13
15
N
Counter Reset
Power Down
Function
VCO CHARACTERISTICS
Data Field
_12
(Continued)
14
N
SHIFT REGISTER BIT LOCATION
3, and must be
_11
13
N
PWDN
N_20
_10
12
12
N
11 10
_9
N
_8
N
swallow counter +2; NB_CNTR
(0.5 GHz to 1.2 GHz)
NA_CNTR[4:0]
DS101124-4
_7
N
9
Asynchronous
Power Down
Powered Up
Operation
_6
N
8
Normal
16/17
0
_5
N
7
_4
N
6
_3
FRAC_CNTR[3:0]
N
5
PRESC_SEL
IN
_2
N
4
input (to a high impedance
N_19
(1.2 GHz to 2.5 GHz)
_1
IN
N
3
Powered Down
Least Significant Bit
Synchronous
Power Down
pin reverts to a high
(NA_CNTR +2).
_0
Reset
32/33
N
2
1
Address Field
1
1
0
1