LMX2487E National Semiconductor Corporation, LMX2487E Datasheet - Page 31

• Manufacturer Part Number: LMX2487E
• Description: 7.5 Ghz High Performance Delta-sigma Low Power Dual Pllatinum? Frequency Synthesizers With 3.0 Ghz Integer Pll
• Manufacturer: National Semiconductor Corporation

REGISTER
2.5 R4 REGISTER
This register controls the conditions for the RF PLL in Fastlock.
2.5.1 MUX[3:0] Frequency Out & Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
2.5.2 IF_P -- IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
2.5.3 RF_CPP -- RF PLL Charge Pump Polarity
2.5.4 IF_CPP -- IF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a negative phase
detector polarity.
R4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATPU
23
IF_P
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
22 21 20 19 18 17 16 15 14 13
0
MUX[3:0]
1
RF_CPP
IF_CPP
0
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
DITH
[1:0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
[1:0]
FM
DATA[19:0]
IF Prescaler
0
16/17
8/9
High Impedance
31
OSC_
Output Type
Open Drain
Open Drain
Open Drain
2X
12
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
OSC_
OUT
11
CPP
IF_
10
RF Charge Pump Polarity
IF Charge Pump Polarity
General purpose output, Logical “High”
General purpose output, Logical “Low”
Positive (Default)
CPP
RF_
9
Negative
Negative
Positive
RF & IF Analog Lock Detect
RF & IF Analog Lock Detect
RF & IF Digital Lock Detect
RF R Divider divided by 2
RF N Divider divided by 2
IF R Divider divided by 2
IF N Divider divided by 2
IF_P
RF Analog Lock Detect
RF Analog Lock Detect
RF Digital Lock Detect
IF Analog Lock Detect
IF Analog Lock Detect
Maximum Frequency
IF Digital Lock Detect
8
Output Description
7 6 5 4
800 MHz
800 MHz
Disabled
MUX
[3:0]
State
State
C3 C2 C1 C0
3
1
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2
0
1
0
0
1