LMX2487E National Semiconductor Corporation, LMX2487E Datasheet - Page 24

• Manufacturer Part Number: LMX2487E
• Description: 7.5 Ghz High Performance Delta-sigma Low Power Dual Pllatinum? Frequency Synthesizers With 3.0 Ghz Integer Pll
• Manufacturer: National Semiconductor Corporation

www.national.com
Programming Description
2.0 GENERAL PROGRAMMING INFORMATION
The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program the R counter,
the N counter, and the internal mode control latches. The data format of a typical 24-bit data register is shown below. The control
bits CTL [3:0] decode the register address. On the rising edge of LE, data stored in the shift register is loaded into one of the
appropriate latches (selected by address bits). Data is shifted in MSB first. Note that it is best to program the N counter last, since
doing so initializes the digital lock detector and Fastlock circuitry. Note that initialize means it resets the counters, but it does NOT
program values into these registers. The exception is when 22-bit is not being used. In this case, it is not necessary to program
the R7 register.
2.0.1 Register Location Truth Table
The control bits CTL [3:0] decode the internal register address. The table below shows how the control bits are mapped to the
target control register.
2.0.2 Control Register Content Map
Because the LMX2487E registers are complicated, they are organized into two groups, basic and advanced. The first four registers
are basic registers that contain critical information necessary for the PLL to achieve lock. The last 5 registers are for features that
optimize spur, phase noise, and lock time performance. The next page shows these registers.
C3
x
0
0
0
1
1
1
1
C2
MSB
23
0
1
1
0
0
1
1
x
DATA [21:0]
C1
24
x
1
0
1
0
1
0
1
4 3
CTL [3:0]
2 1
LSB
C0
0
1
1
1
1
1
1
1
0
DATA Location
R0
R1
R2
R3
R4
R5
R6
R7