LMX2487E National Semiconductor Corporation, LMX2487E Datasheet - Page 23

• Manufacturer Part Number: LMX2487E
• Description: 7.5 Ghz High Performance Delta-sigma Low Power Dual Pllatinum? Frequency Synthesizers With 3.0 Ghz Integer Pll
• Manufacturer: National Semiconductor Corporation

never recommended. In this case, the value for R2p is typi-
cally about 80% of what it would be for a second order filter.
Because the fastlock disengagement glitch gets larger and it
is harder to keep the loop filter optimized as the K value be-
comes larger, designing for the largest possible value for K
usually, but not always yields the best improvement in lock
time. To get a more accurate estimate requires more simula-
tion tools, or trial and error.
1.8.3 Capacitor Dielectric Considerations for Lock Time
The LMX2487E has a high fractional modulus and high
charge pump gain for the lowest possible phase noise. One
consideration is that the reduced N value and higher charge
pump may cause the capacitors in the loop filter to become
larger in value. For larger capacitor values, it is common to
have a trade-off between capacitor dielectric quality and
physical size. Using film capacitors or NPO/COG capacitors
yields the best possible lock times, where as using X7R or
Z5R capacitors can increase lock time by 0 – 500%. However,
it is a general tendency that designs that use a higher com-
pare frequency tend to be less sensitive to the effects of
capacitor dielectrics. Although the use of lesser quality di-
electric capacitors may be unavoidable in many circum-
stances, allowing a larger footprint for the loop filter capaci-
tors, using a lower charge pump current, and reducing the
fractional modulus are all ways to reduce capacitor values.
Capacitor dielectrics have very little impact on phase noise
and spurs.
1.9 FRACTIONAL SPUR AND PHASE NOISE CONTROLS
Control of the fractional spurs is more of an art than an exact
science. The first differentiation that needs to be made is be-
tween primary fractional and sub-fractional spurs. The prima-
ry fractional spurs are those that occur at increments of the
channel spacing only. The sub-fractional spurs are those that
occur at a smaller resolution than the channel spacing, usu-
Note 8: For more information concerning delta-sigma PLLs, loop filter design, cycle slip reduction, Fastlock, and many other topics, visit wireless.national.com.
Here there is the EasyPLL simulation tool and an online reference called "PLL Performance, Simulation, and Design", by Dean Banerjee.
23
ally one-half or one-fourth. There are trade-offs between frac-
tional spurs, sub-fractional spurs, and phase noise. The rules
of thumb presented in this section are just that. There will be
exceptions. The bits that impact the fractional spurs are FM
and DITH, and these bits should be set in this order.
The first step to do is choose FM, for the delta sigma modu-
lator order. It is recommended to start with FM = 3 for a third
order modulator and use strong dithering. In general, there is
a trade-off between primary and sub-fractional spurs. Choos-
ing the highest order modulator (FM = 0 for 4th order) typically
provides the best primary fractional spurs, but the worst sub-
fractional spurs. Choosing the lowest modulator order (FM =
2 for 2nd order), typically gives the worst primary fractional
spurs, but the best sub-fractional spurs. Choosing FM = 3, for
a 3rd order modulator is a compromise.
The second step is to choose DITH, for dithering. Dithering
has a very small impact on primary fractional spurs, but a
much larger impact on sub-fractional spurs. The only problem
is that it can add a few dB of phase noise, or even more if the
loop bandwidth is very wide. Disabling dithering (DITH = 0),
provides the best phase noise, but the sub-fractional spurs
are worst (except when the fractional numerator is 0, and in
this case, they are the best). Choosing strong dithering (DITH
= 2) significantly reduces sub-fractional spurs, if not eliminat-
ing them completely, but adds the most phase noise. Weak
dithering (DITH = 1) is a compromise.
The third step is to tinker with the fractional word. Although
1/10 and 400/4000 are mathematically the same, expressing
fractions with much larger fractional numerators often im-
prove the fractional spurs. Increasing the fractional denomi-
nator only improves spurs to a point. A good practical limit
could be to keep the fractional denominator as large as pos-
sible, but not to exceed 4095, so it is not necessary to use the
extended fractional numerator or denominator.
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