MC56F8346 Freescale Semiconductor, Inc, MC56F8346 Datasheet - Page 123

• Manufacturer Part Number: MC56F8346
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

6.5.9.11
Each bit controls clocks to the indicated peripheral.
6.5.9.12
Each bit controls clocks to the indicated peripheral.
6.5.9.13
Each bit controls clocks to the indicated peripheral.
6.5.9.14
Each bit controls clocks to the indicated peripheral.
6.5.9.15
Each bit controls clocks to the indicated peripheral.
6.5.9.16
Each bit controls clocks to the indicated peripheral.
6.5.10
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in
Note:
Freescale Semiconductor
Preliminary
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1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)
If this register is set to something other than the top of memory (EOnCE register space) and the EX bit
in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions
will be affected.
Serial Communications Interface 1 Enable (SCI1)—Bit 5
Serial Communications Interface 0 Enable (SCI0)—Bit 4
Serial Peripheral Interface 1 Enable (SPI1)—Bit 3
Serial Peripheral Interface 0 Enable (SPI0)—Bit 2
Pulse Width Modulator B Enable (PWMB)—1
Pulse Width Modulator A Enable (PWMA)—0
Figure
6-13.
56F8346 Technical Data, Rev. 15
Register Descriptions
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