EVX8AQ160TPY ETC-unknow, EVX8AQ160TPY Datasheet - Page 71

• Manufacturer Part Number: EVX8AQ160TPY
• Description: Adc Quad 1.25gsps 8-bit Lvds 380-pin Ebga
• Manufacturer: ETC-unknow

Table 9-1.
10. Thermal and Moisture Characteristics
10.1
e2v semiconductors SAS 2009
(Fs max)
(TD2)
(TC)
(TPD)
(TRDR)
(TR)
(TF)
(PSRR)
(NRZ)
(IMD)
(NPR)
(VSWR)
Thermal Characteristics
Maximum Sampling
Frequency
Time delay from data
ready to data
Encoding clock period
Pipeline Delay
Data ready reset delay
Rise time
Fall time
Power supply rejection ratio
Nonreturn to zero
Intermodulation distortion
Noise power ratio
Voltage standing wave ratio
Definition of Terms (Continued)
Assumptions:
• No air
• Pure conduction
• No radiation
• Rth Junction bottom of balls = 4.47
• Rth Junction board = 5.28°C/W
• Rth Junction top of case = 2.0°C/W
• Rth Junction top of case with 50 µm thermal grease = 2.7°C/W
• Rth Junction ambient (JEDEC standard, 49 × 49 mm² board size) = 14.1°C/W
• Rth Junction ambient (180 × 170 mm² evaluation board size) = 10.6°C/W
Sampling Frequency for Which ENOB < 6bits
General expression is TD2 = TC2 + TDR – TOD with TC = TC1 + TC2 = 1 encoding clock period.
TC1 = Minimum clock pulse width (high) TC = TC1 + TC2
TC2 = Minimum clock pulse width (low)
Number of clock cycles between the sampling edge of an input data and the associated output data
being made available, (not taking in account the TOD).
Delay between the first rising edge of the external clock after reset (SYNC, SYNCN) and the reset to
digital zero transition of the data ready output signal (XDR, XDRN, where X = A, B, C or D).
Time delay for the output DATA signals to rise from 20% to 80% of delta between low level and high
level.
Time delay for the output DATA signals to fall from 20% to 80% of delta between low level and high
level.
Ratio of input offset variation to a change in power supply voltage.
When the input signal is larger than the upper bound of the ADC input range, the output code is
identical to the maximum code and the out-of-range bit is set to logic one. When the input signal is
smaller than the lower bound of the ADC input range, the output code is identical to the minimum
code, and the out-of-range bit is set to logic one. (It is assumed that the input signal amplitude
remains within the absolute maximum ratings).
The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the worst
third order intermodulation products.
The NPR is measured to characterize the ADC performance in response to broad bandwidth signals.
When applying a notch-filtered broadband white-noise signal as the input to the ADC under test, the
Noise Power Ratio is defined as the ratio of the average out-of-notch to the average in-notch power
spectral density magnitudes for the FFT spectrum of the ADC output sample test.
The VSWR corresponds to the ADC input insertion loss due to input power reflection. For example a
VSWR of 1.2 corresponds to a 20 dB return loss (ie. 99% power transmitted and 1% reflected).
°
C/W
0846G–BDC–11/09
EV8AQ160
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