EVX8AQ160TPY ETC-unknow, EVX8AQ160TPY Datasheet - Page 47

• Manufacturer Part Number: EVX8AQ160TPY
• Description: Adc Quad 1.25gsps 8-bit Lvds 380-pin Ebga
• Manufacturer: ETC-unknow

e2v semiconductors SAS 2009
The extra clock configuration allows to delay the restart of output data and data ready after SYNC. With
this extra clock delay, the validity range of SYNC signal is extended.
Figure 8-4.
Note:
XHD0…XHD7
XHD0…XHD7
SYNC
X refers to A, B, C and D.
Y refers to the number of extra clock that can be added (Y = 0 to 15) with programming delay of ADC data
ready after SYNC
See
XAIN
XDR
XDR
CLK
Section 8.7 ”Quad ADC Digital Interface (SPI)” on page
Output Data and Data Ready with Extra Delay Configuration
TOD + 2 clock cycles
Y clock cycles
TOD + 2 clock cycles
N
TDR + 3 clock cycles
TR + pipeline delay
TOD + pipeline delay
M
TDR + 3 clock cycles
TDR + pipeline delay
50, (register address 0x06).
Y clock cycles
N
0846G–BDC–11/09
Y clock cycles
EV8AQ160
N +1
M
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