XC3S502 Xilinx Corp., XC3S502 Datasheet - Page 32

• Manufacturer Part Number: XC3S502
• Description: Spartan-3 Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Spartan-3 FPGA Family: Functional Description
The
Delay-Locked Loop (DLL), the Digital Frequency Synthe-
sizer (DFS), the Phase Shifter (PS), and the Status Logic.
Each component has its associated signals, as shown in
Figure
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to elimi-
nate clock skew. The main signal path of the DLL consists of
an input stage, followed by a series of discrete delay ele-
ments or taps, which in turn leads to an output stage. This
32
54
DCM
17.
has
four
PSINCDEC
CLKFB
CLKIN
RST
PSCLK
CLKFB
CLKIN
PSEN
functional
RST
Figure 17: DCM Functional Blocks and Associated Signals
Figure 18: Simplified Functional Diagram of DLL
Delay
1
components:
DLL
Delay
2
Shifter
Status
DCM
Phase
Logic
Detection
Control
Phase
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the
DFS
Delay
n-1
path together with logic for phase detection and control
forms a system complete with feedback as shown in
Figure
8
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
PSDONE
CLK0
CLKFX
CLKFX180
LOCKED
STATUS [7:0]
Delay
18.
n
Distribution
Delay
Clock
DS099-2_08_041103
DS099-2_07_040103
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
LOCKED
DS099-2 (v2.2) May 25, 2007
Product Specification
R