XC3S502 Xilinx Corp., XC3S502 Datasheet - Page 203
![no-image](/images/no-image-200.jpg)
XC3S502
Manufacturer Part Number
XC3S502
Description
Spartan-3 Fpga Family Complete Data Sheet
Manufacturer
Xilinx Corp.
Datasheet
1.XC3S502.pdf
(208 pages)
- Current page: 203 of 208
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Table 109: FG1156 Package Pinout (Continued)
Table 110: User I/Os Per Bank for XC3S4000 in FG1156 Package
Table 111: User I/Os Per Bank for XC3S5000 in FG1156 Package
DS099-4 (v2.2) May 25, 2007
Product Specification
VCCAUX CCLK
VCCAUX DONE
VCCAUX HSWAP_EN
VCCAUX M0
VCCAUX M1
VCCAUX M2
VCCAUX PROG_B
VCCAUX TCK
Package Edge
Package Edge
Bank
N/A
Bottom
Bottom
Right
Right
Top
Left
Top
Left
VCCINT
R
XC3S4000
Pin Name
Bank
Bank
I/O
I/O
VCCINT
CCLK
DONE
HSWAP_EN
M0
M1
M2
PROG_B
TCK
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
XC3S5000
Pin Name
Maximum
Maximum
100
100
100
100
I/O
I/O
90
90
88
88
90
90
88
88
96
96
96
96
Number
FG1156
AD24
AL31
AG8
AK4
D31
Y22
AL4
Pin
L11
D4
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
VCCINT
JTAG
Type
I/O
I/O
79
79
80
79
73
73
79
79
89
89
87
87
83
83
87
87
www.xilinx.com
Table 109: FG1156 Package Pinout (Continued)
User I/Os by Bank
Table 110
tributed between the eight I/O banks for the XC3S4000 in
the FG1156 package. Similarly,
available user-I/O pins are distributed between the eight I/O
banks for the XC3S5000 in the FG1156 package.
VCCAUX TDI
VCCAUX TDO
VCCAUX TMS
DUAL
DUAL
Bank
0
0
0
0
6
6
0
0
0
0
0
0
6
6
0
0
All Possible I/O Pins by Type
All Possible I/O Pins by Type
indicates how the available user-I/O pins are dis-
Spartan-3 FPGA Family: Pinout Descriptions
XC3S4000
Pin Name
DCI
DCI
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
TDI
TDO
TMS
XC3S5000
Pin Name
VREF
VREF
Table 111
7
7
6
7
7
7
7
7
7
7
7
7
7
7
7
7
Number
FG1156
H27
E31
Pin
E4
shows how the
GCLK
GCLK
2
2
0
0
2
2
0
0
2
2
0
0
2
2
0
0
JTAG
JTAG
JTAG
Type
203
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