PIC16C770 Microchip Technology Inc., PIC16C770 Datasheet - Page 85

• Manufacturer Part Number: PIC16C770
• Description: 18/20-pin, 8-bit Cmos Microcontrollers With 10/12-bit A/d
• Manufacturer: Microchip Technology Inc.

9.2.4
While in SLEEP mode, the I
receive addresses or data. When an address match or
complete byte transfer occurs, it wakes the processor
from SLEEP (if the SSP interrupt bit is enabled).
9.2.5
A RESET disables the MSSP module and terminates
the current transfer.
FIGURE 9-13:
2002 Microchip Technology Inc.
SDA
SCL
SLEEP OPERATION
EFFECTS OF A RESET
MSSP BLOCK DIAGRAM (I
SDA in
Bus Collision
SCL in
2
C slave module can
Read
Advance Information
MSb
START bit, STOP bit,
Write collision detect
START bit detect,
end of XMIT/RCV
Clock Arbitration
State counter for
STOP bit detect
Acknowledge
Generate
SSPBUF
SSPSR
2
C MASTER MODE)
LSb
Write
9.2.6
Master mode operation supports interrupt generation
on the detection of the START and STOP conditions.
The STOP (P) and START (S) bits are cleared from a
RESET or when the MSSP module is disabled. Control
of the I
bus is idle with both the S and P bits clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit
(SSPIF) to be set (SSP Interrupt, if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated START
Clock
Data Bus
Shift
Internal
PIC16C717/770/771
Set/RESET, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
RESET ACKSTAT, PEN (SSPCON2)
2
C bus may be taken when the P bit is set or the
MASTER MODE
SSPADD<6:0>
SSPM<3:0>,
Baud
Rate
Generator
DS41120B-page 83