PIC16C770 Microchip Technology Inc., PIC16C770 Datasheet - Page 111

• Manufacturer Part Number: PIC16C770
• Description: 18/20-pin, 8-bit Cmos Microcontrollers With 10/12-bit A/d
• Manufacturer: Microchip Technology Inc.

After the A/D module has been configured as desired
and the analog input channels have their correspond-
ing TRIS bits selected for port inputs, the selected
channel must be acquired before conversion is
started. The A/D conversion cycle can be initiated by
setting the GO/DONE bit. The A/D conversion begins
and lasts for 13T
lowed for performing an A/D conversion:
1.
2.
3.
FIGURE 11-3:
2002 Microchip Technology Inc.
Configure port pins:
• Configure Analog Input mode (ANSEL)
• Configure pin as input (TRISA or TRISB)
Configure the A/D module
• Configure A/D Result Format / voltage refer-
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if required)
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
C
ence (ADCON1)
ONVERTER
A/D
AD
. The following steps should be fol-
(R
(R
VOLTAGE
A/D BLOCK DIAGRAM
VOLTAGE
EFERENCE
EFERENCE
V
V
REF
REF
-
+
(I
-)
+)
NPUT VOLTAGE
VCFG<2:0>
VCFG<2:0>
V
AIN
)
AV
AV
DD
SS
VRH
VRL
VRL
4.
5.
6.
7.
8.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRESH and
ADRESL registers will be updated with the partially
completed A/D conversion value. That is, the
ADRESH and ADRESL registers will contain the value
of the current incomplete conversion.
Note:
PIC16C717/770/771
Wait the required acquisition time.
START conversion
• Set GO/DONE bit (ADCON0)
Wait 13T
either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH and
ADRESL), clear ADIF if required.
For next conversion, go to step 1, step 2 or step
3 as required.
Do not set the ADON bit and the GO/
DONE bit in the same instruction. Doing so
will cause the GO/DONE bit to be automat-
ically cleared.
CHS<3:0>
AD
until A/D conversion is complete, by
RA1/AN1
RA2/AN2/V
RA0/AN0
RB1/AN5/SS
RB0/AN4/INT
RA3/AN3/V
DS41120B-page 109
REF
REF
-/VRL
+/VRH