AMIS-30623 AMI Semiconductor, Inc., AMIS-30623 Datasheet - Page 26

• Manufacturer Part Number: AMIS-30623
• Description: Lin Microstepping Motordriver
• Manufacturer: AMI Semiconductor, Inc.

AMIS-30623 LIN Microstepping Motordriver
The <StepLoss> signal is used to block successive motions. Also this signal will be cleared after Vbb > UV1, making updates of
TagPos possible.
The implementation is illustrated in the state diagram below.
In Stop mode 1 AMIS-30623 is in the Stopped state. Because Vbb < UV2 it enters the ShutDown state. Once Vbb > UV1 the Stopped
state will be entered again.
In Stop mode 2 AMIS-30623 is in the GotoPos state. Because Vbb < UV2 the UV2SIG is set and the HardStop state is entered. After
the hardstop motion is finished (HS to Positioner) it enters the Stopped state. UV2SIG = 1 so the TagPos is not copied in Actpos, and
the shutdown stated is entered. Once Vbb > UV1 the Stopped state will be entered again and because TagPos = Actpos C623 moves
to GotoPos again. <UV2SIG>, <CPFail> and <Steploss> are cleared when Vbb > UV1 so HardStop is not entered again.
15.2.8. OTP register
OTP Memory Structure
The table below shows how the parameters to be stored in the OTP memory are located.
Table 17: OTP Memory Structure
Parameters stored at address 0x00 and 0x01 and bit LOCKBT are already programmed in the OTP memory at circuit delivery. They
correspond to the calibration of the circuit and are just documented here as an indication.
Each OPT bit is at ‘0’ when not zapped. Zapping a bit will set it to ‘1’. Thus only bits having to be at ‘1’ must be zapped. Zapping of a bit
already at ‘1’ is disabled. Each OTP byte will be programmed separately (see command SetOTPparam). Once OTP programming is
completed, bit LOCKBG can be zapped, to disable future zapping, otherwise any OTP bit at ‘0’ could still be zapped by using a
SetOTPparam
AMI Semiconductor – June 2006, Rev 3.0
www.amis.com
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
GotoPos
HS = f (UV2SIG, OVC1, OVC2, CPFail, …)
EnableLIN
command.
SecPos10
AbsThr3
SecPos7
DelThr3
Irun3
Vmax3
OSC3
Bit 7
TagPos
HS to Positioner
AbsThr2
SecPos9
SecPos6
DelThr2
Irun2
Vmax2
OSC2
TSD2
Bit 6
HardStop
≠
ActPos
Figure 18: State Diagram Autarkic Under-voltage Handling
AbsThr1
SecPos8
SecPos5
DelThr1
Irun1
Vmax1
OSC1
TSD1
Bit 5
AbsThr0
SecPos4
DelThr0
Stopped
Irun0
Vmax0
Shaft
If UV2SIG = 1 THEN TagPos
26
OSC0
TSD0
Bit 4
GetStatus
GetFullStatus
Vbb > UV1
StepMode1
SecPos3
Ihold3
ELSE copy TagPos
IREF3
Vmin3
Acc3
Bit 3
BG3
PA3
ShutDown
StepMode0
SecPos2
Ihold2
≠
IREF2
Vmin2
Acc2
Bit 2
BG2
PA2
ActPos
=
ActPos
Failsafe
PWM disabled
Motor in HiZ
Ihold1
LOCKBT
IREF1
Vmin1
Acc1
Bit 1
BG1
PA1
Data Sheet
SleepEn
Ihold0
LOCKBG
IREF0
Vmin0
Acc0
Bit 0
BG0
PA0