WM8608 ETC-unknow, WM8608 Datasheet - Page 26

• Manufacturer Part Number: WM8608
• Description: The Wm8608 Comprises A High Performance Multi-channel Pwm Digital Power Amplifier Controller. Simply By Adding Appropriate Power Output Stages A Multi-channel Power Amplifier May Be Built. Six Identical Full Audio Bandwidth Channels, Plus A Reduced B
• Manufacturer: ETC-unknow

WM8608
INPUT PROCESSOR
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Once the WM8608 has acknowledged a correct address, the controller sends the first byte of control
data (B15 to B8, i.e. the WM8608 register address plus the first bit of register data). The WM8608
then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then
sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the
WM8608 acknowledges again by pulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8608 returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
Figure 18 2-Wire Serial Control Interface
The WM8608 has two possible device addresses, which can be selected using the CSB pin.
The WM8608 supports the production of 2.1, 5.1 and 6.1 outputs from stereo, 5.1, 6.1 and 7.1 inputs
according to Table 21 and Table 22.
Table 21 Input Configuration
The RC channel is accepted either in the RL or RR input, or alternatively in both RL and RR inputs.
Register control bit RCCFG (Table 23) determines which option is used.
Table 22 Output Configuration
By default the Subwoofer channel is directed to the SUB output, which is a lower bandwidth channel
operating at half the PWM frequency of the other channels. Optionally, the subwoofer channel can be
redirected to the RC channel at the full bandwidth.
Table 20 2-Wire MPU Interface Address Selection
CONFIG
Stereo
5.1
6.1
7.1
Stereo
2.1
5.1
6.1
CONFIG
SCLK
SDIN
CSB STATE
START
High
Low
FL OUT
FL IN
•
•
•
•
•
•
•
•
DEVICE ADDRESS
FR IN
(7 BITS)
FR OUT
•
•
•
•
•
•
•
•
OUTPUT CONFIGURATIONS
INPUT CONFIGURATIONS
DEVICE ADDRESS
RD / WR
SL IN
BIT
•
•
•
SL OUT
0011010
0011011
•
•
(LOW)
ACK
SR IN
register address and
•
•
•
CONTROL BYTE 1
1st register data bit
SR OUT
(BITS 15 TO 8)
•
•
RL/RC
IN
•
•
FC OUT
(LOW)
ACK
or
•
•
RR/RC
CONTROL BYTE 1
remaining 8 bits of
IN
•
•
(BITS 7 TO 0)
register data
RC OUT
PP Rev 1.5 March 2004
•
FC IN
•
•
•
(LOW)
ACK
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SUB
OUT
LFE
•
•
•
IN
•
•
•
STOP
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