TMC428 ETC-unknow, TMC428 Datasheet - Page 21

• Manufacturer Part Number: TMC428
• Description: Intelligent Triple Stepper Motor Controller With Serial Peripheral Interfaces
• Manufacturer: ETC-unknow

TMC428 DATA SHEET (V. 1.00 / February 12, 2001)
The bits contained in ref_conf control the semantic and the actions of the reference/stop switch modes
concerning interrupt generation as explained later. A stepper motor stops if the reference/stop switch,
which corresponds to the actual driving direction, becomes active. The configuration bits named
DISABLE_STOP_L respectively DISABLE_STOP_R disable these automatic stop functions. If the bit
SOFT_STOP is set, motor stop forced by a reference switch is done within motion parameter limits while
otherwise stopping is abruptly.
The bit REF_RnL (reference switch Right not Left) defines which switch is the reference switch: If set to
‘1’, the right, else (set to ‘0’) the left one is the reference switch. Note: Definition of the reference switch
by the configuration bit REF_RnL has no effect concerning stopping using reference switches as stop
switches if DISABLE_STOP_L=’0’ respectively DISABLE_STOP_R=’0’.
3
1
Table 8 - lp & ref_conf & ramp_mode (rm)
A reference switch indicates a reference position within a given tolerance. The tolerance can be
programmed in units of steps respectively micro steps. When a reference switch is reached, the actual
position can be stored automatically. The read-only status bit lp (latch position waiting) indicates the
status of this automatic storage of the current position triggered by a reference switch tagged event.
interrupt_mask & interrupt_flags (IDX=%1011)
The TMC428 provides one interrupt register of eight flags for each stepper motor. Each interrupt bit can
be disabled individually. The interrupt status nINT is low active. So, if an interrupt condition of one stepper
motor becomes active, nINT is set to low (‘0’) and it remains low until all interrupt bits– selected by
interrupt masks –of all stepper motors become inactive. If the interrupt status is inactive, nINT is high
(‘1’). The interrupt status is mapped to the most significant bit (31) of each datagram send back to the µC
(see page 10) and it is available at the SDO_C pin of the TMC428 if the pin nSCS_C is low.
Copyright © 2000, TRINAMIC Microchips GmbH
0
TRINAMIC
M I C R O C H I P S
3
0
smda
2
9
ADDRESS
2
8
1 0 1 0
2
7
2
6
2
5
2
4
32 bit DATAGRAM send from a µC to the TMC428
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
DATA
1
2
lp
1
1
ref_conf
1
0
9 8 7 6 5 4 3 2 1 0
rm
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