ATA5823 ATMEL Corporation, ATA5823 Datasheet - Page 91

• Manufacturer Part Number: ATA5823
• Description: Uhf Ask/fsk Transceiver Ata5823 Ata5824
• Manufacturer: ATMEL Corporation

20. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for T
V
4829D–RKE–06/06
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
VS2
15.5
15.6
15.7
16.1
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
No.
16
17
= V
VSINT
Parameters
Bit-rate range
Minimum time period
between edges at pin
SDO_TMDO in RX
transparent mode
Edge-to-edge time
period of the data signal
for full sensitivity in RX
mode
TX Mode
Start-up time
Configuration of the Transceiver with 4-wire Serial Interface
CS set-up time to rising
edge of SCK
SCK cycle time
SDI_TMDI set-up time
to rising edge of SCK
SDI_TMDI hold time
from rising edge of SCK
SDO_TMDO enable
time from rising edge of
CS
SDO_TMDO output
delay from falling edge
of SCK
SDO_TMDO disable
time from falling edge of
CS
CS disable time period
Time period SCK low to
CS high
= 4.4V to 5.25V (car application), typical values at V
Test Conditions
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
XLIM = 0
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
XLIM = 1
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
From IDLE mode
C
L
= 10 pF
amb
= –40°C to +105°C. V
33, 35
32, 33
32, 33
31, 35
31, 35
31, 33
33, 35
Pin
31
33
35
VS1
= V
BR_Range
VS1
T
T
VS2
T
T
T
T
T
Symbol
SCK_setup1
Out_disable
Out_enable
T
CS_disable
DATA_min
Out_delay
CS_setup
T
T
T
T
= V
Startup
= V
Setup
DATA
Cycle
Hold
VS2
VSINT
= V
= 3V and T
VSINT
T
10
Min.
XDCLK
200
100
250
250
250
1.0
2.0
4.0
8.0
1.5
T
1.5
T
50
25
2
= 2.15V to 3.6V (battery application), and
DCLK
DCLK
amb
ATA5823/ATA5824
331.5
= 25°C unless otherwise specified.
Typ.
T
DCLK
331.5
Max.
10.0
20.0
62.5
500
250
125
250
250
250
T
2.5
5.0
DCLK
Kbit/s
Unit
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
µs
ns
Type*
A
A
B
A
A
A
C
C
C
C
C
A
C
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