ATA5823 ATMEL Corporation, ATA5823 Datasheet - Page 57

• Manufacturer Part Number: ATA5823
• Description: Uhf Ask/fsk Transceiver Ata5823 Ata5824
• Manufacturer: ATMEL Corporation

Figure 14-5. Timing Diagram for Failed Bit-check (Condition CV_Lim < Lim_min)
Figure 14-6. Timing Diagram for Failed Bit-check (Condition: CV_Lim
14.1.6
4829D–RKE–06/06
Bit-check counter
Bit-check counter
Duration of the Bit-check
(Lim_min = 14, Lim_max = 24)
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
RX_ACTIVE
Demod_Out
Demod_Out
Bit-check
Bit-check
Start-up mode
Start-up mode
T
T
Startup_Sig_Proc
Startup_Sig_Proc
If no transmitter is present during the Bit-check, the output of the ASK/FSK demodulator delivers
random signals. The Bit-check is a statistical process and T
fore, an average value for T
the selected bit-rate range and on T
T
In the presence of a valid transmitter signal, T
nal, f
longer period for T
Bit-check
0
0
Signal
resulting in a lower current consumption in RX polling mode.
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112
, and the count of the bits, N
Bit-check mode
Bit-check
Bit check failed (CV_Lim < Lim_min)
T
Bit-check
requiring a higher value for the transmitter pre-burst T
1/2 bit
Bit-check mode
Bit-check
T
Bit-check
is given in the electrical characteristics. T
1/2 bit
XDCLK
Bit-check failed (CV_Lim
Bit-check
131415161718192021222324
. A higher bit-rate range causes a lower value for
. A higher value for N
Bit-check
Lim_max)
is dependent on the frequency of that sig-
Sleep mode
Bit-check
ATA5823/ATA5824
Lim_min)
T
Sleep
0
varies for each check. There-
Bit-check
Sleep mode
T
Sleep
0
thereby results in a
Bit-check
Preburst
depends on
.
57