ATA5823 ATMEL Corporation, ATA5823 Datasheet - Page 65

• Manufacturer Part Number: ATA5823
• Description: Uhf Ask/fsk Transceiver Ata5823 Ata5824
• Manufacturer: ATMEL Corporation

Figure 14-12. TX Buffer FD Mode
4829D–RKE–06/06
Preburst (FF hex)
Preburst (FF hex)
Preburst (FF hex)
Preburst (FF hex)
Preburst and Start bit (FE hex)
Synchronization Byte 1 (FF hex)
Synchronization Byte 2 (00 hex)
Synchronization Byte 3 (00 hex)
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Data Byte 8
If the time T
The master activates the power amplifier (PA) and starts transmitting the preburst, startbit, syn-
chronization pattern and data block, when the PLL is locked and at least N bytes are in the TX
Buffer. Bit 0 to bit 4 in the command Write TX/RX Data Buffer defines the value N (0 N 16;
see section
If the PLL is locked, the slave activates the PA and enables the analog signal processing. After
T
the Bit-check. If the Bit-check was successful, the start bit was detected and at least N Bytes are
in the TX Buffer, the slave starts transmitting the synchronization pattern and the data block.
While transmitting the synchronization pattern, a synchronization procedure synchronizes both
transceivers. Thus master and slave are synchronized while transmitting the data block.
If the TX buffer is empty, an interrupt will be issued and the PA will be switched off after the time
T
path in master and slave.
While transmitting the data block, the receiving data is EX-OR-ed with the transmitting data and
the result is written in the RX Buffer. Thus, after the FD operation the TX data of the slave is in
the RX buffer of the master and the TX data of the master is in the RX Buffer of the slave.
After recognizing the interrupt, the microcontroller can read out the received data from the
TX/RX data buffer. During writing the command “Read TX/RX Data Buffer” the number of
received bytes in the buffer is issued on pin SDO_TMDO.
After reading the TX/RX Data Buffer the transceiver should be set to the IDLE mode.
Startup-sig-proc-fd
Delay
MSB
(168
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
39 Bits Preburst
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
TX Buffer Master
1 Start bit
3 Bytes Synchronization Pattern
8 Bytes Data
Startup-PLL-fd
“Command Structure” on page
T
DCLK
(546
). T
Delay
(798.5
T
LSB
DCLK
is implemented because of different internal delays in the RX signal
) the analog signal processing is settled and the slave begins with
T
DCLK
) is elapsed the PLL is enabled and locked.
MSB
0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
3 Bytes Synchronization Pattern
8 Bytes Data
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
49).
TX Buffer Slave
LSB
ATA5823/ATA5824
Synchronization Byte 1 (00 hex)
Synchronization Byte 2 (7F hex)
Synchronization Byte 3 (FF hex)
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Data Byte 8
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