MCP6S92 Microchip Technology Inc., MCP6S92 Datasheet - Page 22

• Manufacturer Part Number: MCP6S92
• Description: Single-ended, Rail-to-rail I/o, Low-gain Pga
• Manufacturer: Microchip Technology Inc.

5.2
The analog functions are programmed through the SPI
interface using 16-bit words (see Figure 5-1 and
Figure 5-2). This data is sent to two of three 8-bit regis-
ters: Instruction register (Register 5-1), Gain register
(Register 5-2) and Channel register (Register 5-3).
There are no power-up defaults for these three
registers.
5.2.1
After power up, the registers contain random data that
must be initialized. Sending valid gain and channel
selection commands to the internal registers puts valid
data into those registers. Also, the internal state
machine starts in an arbitrary state. Toggling the Chip
Select pin (CS) from high to low, then back to high
again, puts the internal state machine in a known, valid
condition (this can be done by entering any valid
command).
REGISTER 5-1:
 2004 Microchip Technology Inc.
Registers
bit 7-5
bit 4-1
bit 0
ENSURING VALID DATA IN THE
REGISTERS
bit 7
W-0
M2
INSTRUCTION REGISTER
M2-M0: Command bits
000 = NOP (Note 1)
001 = PGA enters Shutdown mode as soon as a full 16-bit word is sent and CS is raised.
010 = Write to register.
011 = NOP (reserved for future use) (Note 1)
1XX = NOP (reserved for future use) (Note 1)
Unimplemented: Read as ‘0’ (reserved for future use)
A0: Indirect Address bit
1 = Addresses the Channel register
0 = Addresses the Gain register
Note 1:
Legend:
R = Readable bit
-n = Value at POR
W-0
M1
2:
(Notes 1 and 2)
All other bits in the 16-bit word (including A0) are “don’t cares.”
The device exits Shutdown mode when a valid command (other than NOP or
Shutdown) is sent and CS is raised; that valid command will be executed.
Shutdown does not toggle.
W-0
M0
W = Writable bit
‘1’ = Bit is set
U-x
—
After power-up, and when the power supply voltage
dips below the minimum valid V
nal register data and state machine may need to be
reset. This is accomplished as described before. Use
an external system supervisor to detect these events
so that the microcontroller will reset the PGA state and
registers.
A 0.1 µF bypass capacitor mounted as close as
possible to the V
immunity.
5.2.2
The Instruction register has 3 command bits and 1 indi-
rect address bit; see Register 5-1. The command bits
include a NOP (000) to support daisy-chaining (see
Section 5.3 “Daisy-Chain Configuration”); the other
NOP commands shown should not be used (they are
reserved for future use). The device is brought out of
Shutdown mode when a valid command, other than
NOP or Shutdown, is sent and CS is raised.
U-x
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
INSTRUCTION REGISTER
U-x
—
DD
MCP6S91/2/3
pin provides additional transient
U-x
—
DD
x = Bit is unknown
(V
W-0
A0
DS21908A-page 22
DD_VAL
bit 0
), the inter-