MCP6S92 Microchip Technology Inc., MCP6S92 Datasheet - Page 18

• Manufacturer Part Number: MCP6S92
• Description: Single-ended, Rail-to-rail I/o, Low-gain Pga
• Manufacturer: Microchip Technology Inc.

4.0
The MCP6S91/2/3 family of Programmable Gain
Amplifiers (PGA) is based on simple analog building
blocks (see Figure 4-1). Each of these blocks will be
explained in more detail in the following subsections.
FIGURE 4-1:
4.1
The MCP6S91 has one input, while the MCP6S92 and
MCP6S93 have two inputs (see Figure 4-1).
For the lowest input current, float unused inputs. Tying
these pins to a voltage near the active channel’s bias
voltage also works well. For simplicity, they can be tied
to V
The one-channel MCP6S91 has approximately the
same input bias current as the two-channel MCP6S92
and MCP6S93.
The input offset voltage mismatch between channels
( V
transmission gates that have drain-source (channel)
resistance, but no offset voltage. The histogram in
Figure 2-8 reflects the measurement repeatability
(i.e., noise power bandwidth) rather than the actual
mismatch. Reducing the measurement bandwidth will
produce a more narrow histogram and give an aver-
age closer to 0 µV.
 2004 Microchip Technology Inc.
CH0
CH1
SCK
MCP6S91 – One input (CH0), no SO pin
MCP6S92 – Two inputs (CH0, CH1), V
MCP6S93 – Two inputs (CH0, CH1)
SO
CS
OS
SS
SI
) is, ideally, 0 µV. The input MUX uses CMOS
or V
ANALOG FUNCTIONS
Input MUX
SPI™
Logic
DD
MUX
, but the input current may increase.
internally to V
V
SS
Switches
PGA Block Diagram.
Gain
V
DD
SS
8
, no SO pin
V
REF
R
R
G
F
REF
V
tied
OUT
4.2
The internal op amp gives the right combination of
bandwidth, accuracy and flexibility.
4.2.1
The internal op amp has three compensation capaci-
tors (comp. caps.) connected to a switching network.
They are selected to give good small-signal bandwidth
at high gains and good slew rates (full-power band-
width) at low gains. The change in bandwidth as gain
changes is between 2 and 12 MHz. Refer to Table 4-1
for more information.
TABLE 4-1:
4.2.2
The input stage of the internal op amp uses two differ-
ential input stages in parallel; one operates at low V
(input voltage), while the other operates at high V
With this topology, the internal inputs can operate to
0.3V past either supply rail. The input offset voltage is
measured at both V
ensure proper operation.
The transition between the two input stages occurs
when V
linearity, avoid this region of operation.
Note 1:
(V/V)
Gain
10
16
32
1
2
4
5
8
2:
3:
IN
Internal
Medium
Medium
Medium
Medium
Internal Op Amp
Comp.
Large
Large
Small
Small
Cap.
FPBW is the Full-Power Bandwidth.
These numbers are based on V
No changes in DC performance
(e.g., V
compensation capacitor.
BW is the closed-loop, small signal -3 dB
bandwidth.
V
COMPENSATION CAPACITORS
RAIL-TO-RAIL CHANNEL INPUTS
DD
– 1.5V. For the best distortion and gain
GAIN VS. INTERNAL
COMPENSATION
CAPACITOR
OS
GBWP
MCP6S91/2/3
(MHz)
IN
Typ.
) accompany a change in
12
12
20
20
20
20
64
64
= V
SS
– 0.3V and V
(V/µs)
Typ.
SR
4.0
4.0
22
22
11
11
11
11
DS21908A-page 18
FPBW
(MHz)
Typ.
0.30
0.30
0.70
0.70
0.70
0.70
1.6
1.6
DD
DD
+ 0.3V to
= 5.0V.
(MHz)
Typ.
BW
2.4
2.0
2.0
12
10
6
7
5
IN
IN
.