RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 26
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RS8234
Manufacturer Part Number
RS8234
Description
Atm Servicesar Plus With Xbr Traffic Management
Manufacturer
Mindspeed Technologies
Datasheet
1.RS8234.pdf
(401 pages)
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18
List of Figures
Figure 5-15.
Figure 5-16.
Figure 5-17.
Figure 5-18.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 6-4.
Figure 6-5.
Figure 6-6.
Figure 6-7.
Figure 6-8.
Figure 6-9.
Figure 6-10.
Figure 6-11.
Figure 6-12.
Figure 6-13.
Figure 6-14.
Figure 6-15.
Figure 6-16.
Figure 6-17.
Figure 6-18.
Figure 6-19.
Figure 6-20.
Figure 6-21.
Figure 6-22.
Figure 6-23.
Figure 7-1.
Figure 7-2.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Figure 10-6.
Figure 10-7.
Figure 10-8.
Figure 10-9.
Figure 10-10.
Status Queue Structure Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
VPI/VCI Channel Lookup Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
Reassembly VCC Table Entry Lookup Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
LECID Table, Illustrated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54
Non-ABR Cell Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
ABR Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Schedule Table with Size = 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Schedule Slot Formats With USE_SCH_CTRL Not Asserted . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Schedule Slot Formats With USE_SCH_CTRL Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
One Possible Scheduling Priority Scheme with the RS8234 . . . . . . . . . . . . . . . . . . . . . . . 6-10
Assigning CBR Cell Slots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Introduction of CDV at the ATM/PHY Layer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Schedule Table with Slot Conflicts at Different CBR Rates . . . . . . . . . . . . . . . . . . . . . . . . 6-13
CDV Caused by Schedule Table Size at Certain CBR Rates . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Another Possible Scheduling Priority Scheme with the RS8234 . . . . . . . . . . . . . . . . . . . . 6-20
ABR Service Category Feedback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
RS8234 ABR-ER Feedback Loop (Source Behavior) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
RS8234 ABR-ER Feedback Generation (Destination Behavior) . . . . . . . . . . . . . . . . . . . . . 6-24
Steady State ABR-ER Cell Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Cell Type Interleaving on ABR-ER Cell Stream. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Cell Decision Table for Nrm = 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
Backward_RM Flow Control, Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
Relative Rate (RR) RATE_INDEX Candidate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
Explicit Rate (ER) RATE_INDEX Candidate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
Dynamic Traffic Shaping from RM Cell Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
ABR Linkage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51
Head and Tail Pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
OAM Cell Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Functional Blocks for PM Segmentation and Reassembly. . . . . . . . . . . . . . . . . . . . . . . . . 7-11
LIttle Endian Aligned Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Little Endian Misaligned Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Big Endian Aligned Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Big Endian Misaligned Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
RS8234 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
0.5 MB SRAM Bank Utilizing by_8 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
1 MB SRAM Bank Utilizing by_16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
RS8234—Local Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Local Processor Single Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Local Processor Single Read Cycle with Arbitration Wait States . . . . . . . . . . . . . . . . . . . . 10-7
Local Processor Double Read with Wait States Inserted . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Local Processor Single Write with One Wait State by_16 SRAM. . . . . . . . . . . . . . . . . . . . 10-9
Local Processor Quad Write, No Wait States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
i960CA/CF to the RS8234 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
RS825x and SAR (RS8234) Interface (Standalone Operation) . . . . . . . . . . . . . . . . . . . . 10-14
RS8234/PHY Functional Timing with Inserted Wait States . . . . . . . . . . . . . . . . . . . . . . . 10-15
RS8234/RS825x Read/Write Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234
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