STE2004S STMicroelectronics, STE2004S Datasheet - Page 28

• Manufacturer Part Number: STE2004S
• Description: 102 x 65 Single Chip Lcd Controller / Driver
• Manufacturer: STMicroelectronics

STE2004S
during the last write access, is set to a logic 0, the byte read is the status byte.
Figure 33. Communication Protocol
4.2 SERIAL INTERFACES
STE2004S can feature three different serial synchronized interfaces with the host controller. It is possible to se-
lect a 3-lines SPI, a 4-lines SPI or 3-line 9 bits Serial Interface.
4.2.1 4-lines SPI interface
STE2004S 4-lines serial interface is a bidirectional link between the display driver and the application supervi-
sor.
It consists of four lines: one/two for data signals (SDIN, SOUT), one for clock signals (SCLK), one for the pe-
ripheral enable (CS) and one for mode selection (SD/C).
The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial peripheral power
consumption is zero. While CS pin is high the serial interface is kept in reset.
The STE2004S is always a slave on the bus and receive the communication clock on the SCLK pin from the
master.
Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge.
SD/C line status indicates whether the byte is a command (SD/C =0) or a data (SD/C =1); SD/C line is read on
the eighth SCLK clock pulse during every byte transfer.
If CS stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte
at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal
registers are cleared.
If CS is low after the positive edge of RES, the serial interface is ready to receive data.
Throughout SDOUT can be read the driver I
allows to read I
steady state and during data write.
It is possible to short circuit SDOUT and SDIN and read I2C address or status Byte without any additional lines.
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WRITE MODE
S
S
READ MODE
2
SLAVE ADDRESS
0 1 1 1 1
0 1 1 1 1
C slave address or Status byte is reported in Fig. 34 & 35. SDOUT is in High impedance in
S
A
1
S
A
1
DRIVER ACK
DRIVER ACK
S
A 0 A
S
A 1 A
0
0
R/W
R/W
Co
1 DC Control Byte
COMMAND WORD
MASTER ACK
DRIVER ACK
2
C slave address or the status byte. The Command sequence that
A
P
DATA Byte
SLAVE ADDRESS
0 1 1 1 1
DRIVER ACK
DRIVER
A 0
Co
CONTROL BYTE
DC Control Byte
S
A
1
S
A
0
LAST
W
R
/
DRIVER ACK
A
C
o
D
C
CONTROL BYTE
MSB........LSB
0 0 0
N> 0 BYTE
DATA Byte
H
E
[1]
H
DRIVER ACK
[0]
H
LR0008
A
A P