STE2004S STMicroelectronics, STE2004S Datasheet - Page 27

• Manufacturer Part Number: STE2004S
• Description: 102 x 65 Single Chip Lcd Controller / Driver
• Manufacturer: STMicroelectronics

Figure 31. Bit transfer and START,STOP conditions definition
Figure 32. Acknowledgment on the I
4.1.1 Communication Protocol
The STE2004S is an I
are allowed.
Four are the device addresses available for the device. All have in common the first 5 bits (01111). The
two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or
to a logic 1.
To start the communication between the bus master and the slave LCD driver, the master must initiate a
START condition. Following this, the master sends an 8-bit byte, on the SDA bus line (Most significant bit
first). This consists of the 7-bit Device select Code, and the 1-bit Read/Write Designator (R/W).
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I
transfer.
4.1.1.1 Writing Mode.
If the R/W bit is set to logic 0 the STE2004S is set to be a receiver. After the slaves acknowledge one or
more command word follows to define the status of the device.
A command word is composed by three bytes. The first is a control byte which defines the Co and D/C
values, the second and third are data bytes. The Co bit is the command MSB and defines if after this com-
mand will follow two data bytes and an other command word or if will follow a stream of data (Co = 1 Com-
mand word, Co = 0 Stream of data). The D/C bit defines whether the data byte is a command or RAM data
(D/C = 1 RAM Data, D/C = 0 Command).
If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the
following data byte will be stored in the data RAM at the location specified by the data pointer.
Every byte of a command word must be acknowledged by all addressed units.
After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2004S
Display RAM starting at the address specified by the data pointer. The data pointer is automatically up-
dated after every byte written and in the end points to the last RAM location written.
Every byte must be acknowledged by all addressed units.
4.1.1.2 Reading Mode.
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
SCLK FROM
MASTER
2
CLOCK
C slave. The access to the device is bi-directional since data write and status read
DATA
CONDITION
START
START
MSB
1
2
C-bus
DATA VALID
DATA LINE
STABLE
DATA ALLOWED
CHANGE OF
2
8
LSB
CONDITION
STOP
ACKNOWLEDGEMENT
CLOCK PULSE FOR
9
LR0069
LR0070
STE2004S
2
C-bus
27/66