STE2002DIE1 STMicroelectronics, STE2002DIE1 Datasheet - Page 23
STE2002DIE1
Manufacturer Part Number
STE2002DIE1
Description
81 x 128 Single Chip LCD Controller/Driver
Manufacturer
STMicroelectronics
Datasheet
1.STE2002DIE1.pdf
(51 pages)
- Current page: 23 of 51
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If SCE stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte
at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal
registers are cleared.
If SCE is low after the positive edge of RES, the serial interface is ready to receive data.
Throughout SOUT can be read only the driver I
I
It is possible to short circuit DOUT and SDIN and read I2C address without any additional lines.
Figure 32. Serial bus protocol - one byte transmission
Figure 33. Serial bus protocol - several byte transmission
Figure 34. Serial bus protocol - several byte transmission
2
SCLK
SDIN
SCE
D/C
C slave address is reported in Fig. 34 & 35. SOUT is in High impedance in steady state and during data write.
SOUT
SCLK
SDIN
SCE
D/C
SCLK
SDIN
SCE
D/C
DB7
DB7
DB6
MSB
DB6
DB5
DB5
DB4
Command Write
DB4
High-Z
DB3
DB3
DB2
DB2
DB1
DB1
2
DB0
DB0
C slave address. The Command sequence that allows to read
Don't
Care
DB7
DB7
Don't
Care
DB6
DB6
Don't
Care
DB5
DB5
I2C Address Read
Don't
Care
DB4
DB4
Don't
Care
DB3
DB3
Don't
Care
DB2
DB2
Don't
Care
DB1
DB1
Don't
Care
DB0
DB0
LSB
DB7
DB7
High-Z
DB6
STE2002
DB6
D00IN1159
D00IN1160
D00IN1160
DB5
DB5
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