STG3000X STMicroelectronics, STG3000X Datasheet - Page 2

• Manufacturer Part Number: STG3000X
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

RIVA 128
1
1
2
3
4
5
6
7
8
9
2/77
REVISION HISTORY ......................................................................................................................
RIVA 128 300PBGA DEVICE PINOUT ..........................................................................................
PIN DESCRIPTIONS ......................................................................................................................
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
OVERVIEW OF THE RIVA 128 ......................................................................................................
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10 CUSTOMER EVALUATION KIT............................................................................................
3.11 TURNKEY MANUFACTURING PACKAGE...........................................................................
ACCELERATED GRAPHICS PORT (AGP) INTERFACE .............................................................
4.1
4.2
PCI 2.1 LOCAL BUS INTERFACE.................................................................................................
5.1
5.2
SGRAM FRAMEBUFFER INTERFACE.........................................................................................
6.1
6.2
6.3
6.4
VIDEO PLAYBACK ARCHITECTURE...........................................................................................
7.1
VIDEO PORT ..................................................................................................................................
8.1
8.2
8.3
8.4
8.5
8.6
BOOT ROM INTERFACE...............................................................................................................
ACCELERATED GRAPHICS PORT (AGP) INTERFACE .....................................................
PCI 2.1 LOCAL BUS INTERFACE ........................................................................................
SGRAM FRAMEBUFFER INTERFACE ................................................................................
VIDEO PORT.........................................................................................................................
DEVICE ENABLE SIGNALS..................................................................................................
DISPLAY INTERFACE ..........................................................................................................
VIDEO DAC AND PLL ANALOG SIGNALS ..........................................................................
POWER SUPPLY ..................................................................................................................
TEST......................................................................................................................................
BALANCED PC SYSTEM......................................................................................................
HOST INTERFACE ...............................................................................................................
2D ACCELERATION .............................................................................................................
3D ENGINE ...........................................................................................................................
VIDEO PROCESSOR............................................................................................................
VIDEO PORT.........................................................................................................................
DIRECT RGB OUTPUT TO LOW COST PAL/NTSC ENCODER .........................................
SUPPORT FOR STANDARDS..............................................................................................
RESOLUTIONS SUPPORTED..............................................................................................
RIVA 128 AGP INTERFACE .................................................................................................
AGP BUS TRANSACTIONS..................................................................................................
RIVA 128 PCI INTERFACE ...................................................................................................
PCI TIMING SPECIFICATION...............................................................................................
SGRAM INITIALIZATION ......................................................................................................
SGRAM MODE REGISTER ..................................................................................................
LAYOUT OF FRAMEBUFFER CLOCK SIGNALS ................................................................
SGRAM INTERFACE TIMING SPECIFICATION ..................................................................
VIDEO SCALER PIPELINE ...................................................................................................
VIDEO INTERFACE PORT FEATURES ...............................................................................
BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC ..............................
TIMING DIAGRAMS ..............................................................................................................
656 MASTER MODE ............................................................................................................. 46
VBI HANDLING IN THE VIDEO PORT .................................................................................
SCALING IN THE VIDEO PORT ...........................................................................................
TABLE OF CONTENTS
128-BIT 3D MULTIMEDIA ACCELERATOR
10
11
11
11
12
12
12
13
13
13
13
14
14
15
16
16
22
22
29
31
31
32
32
37
38
40
40
41
42
47
47
48
23
4
5
6
6
6
8
8
9
9
9
9