CC2400 Chipcon AS, CC2400 Datasheet - Page 61

• Manufacturer Part Number: CC2400
• Description: 2.4 GHz RF Transceiver
• Manufacturer: Chipcon AS

MANOR (0x13) - Manual signal OR override register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MDMTST0 (0x14) - Modem Test Register 0
15:14
13
12
11
10
•
Chipcon AS
Bit
Bit
3
See footnote for MANAND register (address 0x0D) for description of the use of this register.
Field Name
VGA_RESET_N
LOCK_STATUS
BALUN_CTRL
RXTX
PRE_PD
PA_N_PD
PA_P_PD
DAC_LPF_PD
BIAS_PD
XOSC16M_PD
CHP_PD
FS_PD
ADC_PD
VGA_PD
RXBPF_PD
LNAMIX_PD
Field Name
-
TX_PRNG
TX_1MHZ_OFFSET_N
INVERT_DATA
AFC_ADJUST_ON_PACKET
SmartRF
®
CC2400 PRELIMINARY Datasheet (rev. 1.1), 2003-10-02
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W0
R/W
R/W
R/W
R/W
SmartRF
Description
Overrides the VGA_RESET_N used to reset the peak detectors
in the VGA in the RX chain.
Overrides the LOCK_STATUS top-level signal that indicates
whether VCO lock is achieved or not.
Overrides the BALUN_CTRL signal that controls whether the PA
should receive its required external biasing (1) or not (0) by
controlling the RX/TX output switch.
Overrides the RXTX signal that controls whether the LO buffers
(0) or PA buffers (1) should be used.
Power down of prescaler.
Power down of PA (negative path).
Power down of PA (positive path). When
PA_P_PD
Power down of TX DACs.
Power down control of global bias generator + XOSC clock
buffer.
Power down control of 16 MHz XOSC core.
Power down control of charge pump.
Power down control of VCO, I/Q generator, LO buffers.
Power down control of the ADCs.
Power down control of the VGA.
Power down control of complex band-pass receive filter.
Power down control of LNA, down-conversion mixers and front-
end bias.
Description
Reserved, write as 0.
When set, the transmitted data is taken from a 10-bit PRNG
instead of from the DIO pin in un-buffered mode or from the
FIFO in buffered mode.
Determines TX IF frequency:
0: 1 MHz (Not used)
1: 0 MHz (During initialization this bit must be set to a logical ’1’.)
When this bit is set the data are inverted (internally) before
transmission, and inverted after reception.
When this bit is set to '1', modem parameters are adjusted for
slow tracking of the received signal as opposed to quick
acquisition when a packet is received in RX.
3
=1 the up-conversion mixers are in power down.
®
CC2400
Page 61 of 73
PA_N_PD
=1 and