CC2400 Chipcon AS, CC2400 Datasheet - Page 26

• Manufacturer Part Number: CC2400
• Description: 2.4 GHz RF Transceiver
• Manufacturer: Chipcon AS

Data Buffering
The
un-buffered data interface. The data
buffering mode is controlled by the
GRMDM.PIN_MODE[1:0]
address 0x20).
In un-buffered mode a synchronous data
clock is provided by
pin, and the DIO pin is used as data
input/output (see Figure 8).
Buffered mode
In the buffered mode a 32-byte First-in
First-Out (FIFO) register block is used for
data to be transmitted and data received.
The FIFO is accessed through the
FIFOREG register (address 0x70) using
the SPI interface. Multiple bytes can be
written to the FIFO without repeating the
address if the CSn line is held low.
The crystal oscillator must be running
when accessing the FIFO.
By using the FIFO buffer the data can be
transmitted in bursts. The buffered mode
will therefore offload the host controller
keeping the SPI data rate much lower than
the data rate on the air. This gives also a
great advantage in reducing the current
consumption
receiver are enabled only in short periods.
It also allows the SPI to operate faster
than the data rate, providing more time for
the MCU to work between data transfers.
More than 32 bytes can be received if the
FIFO is read during reception. In the same
way
transmitted if new data is written into the
FIFO during transmission. Figure 9 shows
Chipcon AS
CC2400
more
can be used with a buffered or
SmartRF
than
as
the
®
32
CC2400
CC2400 PRELIMINARY Datasheet (rev. 1.1), 2003-10-02
transmitter
bytes
bits
at the DCLK
can
(register
and
be
SmartRF
the ways the FIFO can be used during
transmission.
Buffered mode hardware support
In the buffered mode the FIFO pin can be
used as an interrupt output to assist the
microcontroller in supervising the FIFO.
The FIFO pin can be programmed to give
an interrupt when the FIFO is nearly
empty in TX mode, and nearly full in RX
mode. The threshold (FIFO_THRESHOLD)
is set in INT.FIFO_THRESHOLD[4:0].
In receive mode there will be an interrupt
when the number of received bytes in the
FIFO reaches FIFO_THRESHOLD. The
default value is 30, giving an interrupt
when 30 bytes are received. If the FIFO
becomes full (32 bytes) before it is read,
the reception will be terminated (goes to
idle state).
In transmit mode there will be an interrupt
when the number of bytes left in the FIFO
reaches 32 - FIFO_THRESHOLD. For the
default value this will happen when there
are 2 bytes left. The transmission is
terminated when the FIFO runs empty
(goes to idle state). Note that in order for
the FIFO pin to give an interrupt in
transmit mode the number of bytes must
first exceed 32 - FIFO_THRESHOLD.
The FIFO pin activity is illustrated in
Figure 10.
The INT.FIFO_POLARITY bit sets the
polarity of the interrupt signal.
®
CC2400
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