MSK (Minimum Shift Keying) CML Microcircuits, MSK (Minimum Shift Keying) Datasheet - Page 23

• Manufacturer Part Number: MSK (Minimum Shift Keying)
• Description: Minimum Shift Keying and its Application to Wireless Data Transmission
• Manufacturer: CML Microcircuits

MSK and its Application to Wireless Data Transmission
3.2.3.1 Digital Phase Lock Loop
The PLL aligns the output clock rising edge to the middle of the input NRZ data bit. When the PLL is not aligned with the
incoming data a correction factor is applied to the PLL clock period until it becomes synchronized with the incoming data.
As seen in Figure 29 the output clock starts out of phase with the data and it becomes synchronized by the end of the
plot. In Figure 29 the correction factor used is one 12
_____________________________________________________________________________________
I/O, Variables and Constants
_____________________________________________________________________________________
Pseudo Code for First Order Digital PLL
© 1997 MX COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
input[i]
output[i]
X
N
early
late
counter
reset
reset = 0;
if counter<N/2-(0.5X) and input[0] not equal to input[1]
if counter>N/2+(0.5X ) and input[0] not equal to input[1]
if counter is equal to N - 1 - X and early and NOT late
if counter is N-1 and NOT early and NOT late
if counter is N-1 and early and late
if counter is equal to N - 1+ X
if counter > N/2
then
then
then
then
then
then
then
else
early = 1;
late = 1;
reset = 1;
reset = 1;
reset = 1;
reset = 1;
output = 0;
output = 1;
// current input sample; input is NRZ data
// current output sample; output is clock which locks to NRZ data changes
// the correction factor (Note: for MX-COM MSK modems X = 5% bit time)
// number of samples per symbol
// flag set TRUE if data transition is early
// flag set TRUE is data transition is late
// a general counter
// flag set TRUE when algorithm determines it is time to reset counter
www.mxcom.com Tele: 800 638-5577 910 744-5050
Pseudo-Code Listing 6
clock output
input data
// set output clock phase based on counter state
Figure 29: Bit Synchronization Plot.
1
2
th
of a bit period to more clearly show the locking process
3
23
4
Digital PLL with N=12
Time (Bits)
All trademarks and service marks are held by their respective companies.
5
// set early flag
// set late flag
// apply correction factor
//
// apply no correction
//
// reset on time since flags conflict
// apply correction factor
//
6
Digital PLL
7
by resetting early
by resetting on time
by resetting late
8
Fax: [phone]
9
Doc. # 20830084.001
APPLICATION