MSC8113 Freescale Semiconductor / Motorola, MSC8113 Datasheet - Page 22

• Manufacturer Part Number: MSC8113
• Description: Tri-Core Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Electrical Characteristics
22
Notes:
No.
11a
11b
11c
11d
15a
15b
13
14
10
12
16
17
18
1
1
1.
2.
3.
Hold time for all signals after the 50% level of the REFCLK rising edge
ARTRY/ABB set-up time before the 50% level of the REFCLK rising edge
DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising
edge
AACK set-up time before the 50% level of the REFCLK rising edge
TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge
•
•
Data bus set-up time before REFCLK rising edge in Normal mode
•
•
Data bus set-up time before the 50% level of the REFCLK rising edge in ECC
and PARITY modes
•
•
DP set-up time before the 50% level of the REFCLK rising edge
•
•
TS and Address bus set-up time before the 50% level of the REFCLK rising edge
•
•
Address attributes: TT/TBST/TSZ/GBL set-up time before the 50% level of the
REFCLK rising edge
•
•
PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge
IRQx setup time before the 50% level; of the REFCLK rising edge
IRQx minimum pulse width
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
Guaranteed by design.
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0
3
Characteristic
Table 14. AC Timing for SIU Inputs
3
Ref = CLKIN at 1.1 V
and 100/133 MHz
6.0 + T
0.5
3.1
3.6
3.0
3.5
4.4
1.9
4.2
2.0
8.2
2.0
7.9
4.2
5.5
3.7
4.8
3.7
4.0
REFCLK
Freescale Semiconductor
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns