MSC8113 Freescale Semiconductor / Motorola, MSC8113 Datasheet - Page 19

• Manufacturer Part Number: MSC8113
• Description: Tri-Core Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

2.5.4.1
Asserting
V
2.5.4.2
The MSC8113 has two mechanisms for writing the reset configuration:
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on
Configuration Mode and boot and operating conditions:
Freescale Semiconductor
Configuration pins sampled (Refer to
Section 2.5.4.1 for details).
SPLL state reset
System reset configuration write through
the DSI
System reset configuration write though
the system bus
HRESET driven
SIU registers reset
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and
GPIO)
SRESET driven
SC140 extended cores reset
MQBS reset
DD
•
•
•
•
•
•
•
•
•
•
and
Reset Action/Reset Source
V
Through the direct slave interface (DSI)
Through the system bus. When the reset configuration is written through the system bus, the MSC8113 acts as a
configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is
written, a default configuration word is applied.
RSTCONF
CNFGS
DSISYNC
DSI64
CHIP_ID[0–3]
BM[0–2]
SWTE
MODCK[1–2]
PORESET
DDH
are both at their nominal levels.
Power-On Reset (PORESET) Pin
Reset Configuration
initiates the power-on reset flow.
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0
Table 11. Reset Actions for Each Reset Source
External only
(PORESET)
Power-On
Reset
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PORESET
(Software Watchdog or
Hard Reset (HRESET)
External or Internal
Bus Monitor)
must be asserted externally for at least 16
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
PORESET
External
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Soft Reset (SRESET)
deassertion to define the Reset
Electrical Characteristics
EXTEST, CLAMP, or
Depends on command
JTAG Command:
CLKIN
HIGHZ
Yes
Yes
Yes
No
No
No
No
No
No
cycles after
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