MSC8113 Freescale Semiconductor / Motorola, MSC8113 Datasheet - Page 18

• Manufacturer Part Number: MSC8113
• Description: Tri-Core Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Electrical Characteristics
2.5.4
The MSC8113 has several inputs to the reset logic:
All MSC8113 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.
The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources.
Table 11 summarizes the reset actions that occur as a result of the different reset sources.
18
Power-on reset
(PORESET)
External hard
reset (HRESET)
External soft reset
(SRESET)
Software
watchdog reset
Bus monitor reset
Host reset
command through
the TAP
PLL output frequency (VCO output)
•
•
CLKOUT frequency jitter
CLKOUT phase jitter
Notes:
300 MHz core
400 MHz core
•
•
•
•
•
•
Name
Power-on reset (
External hard reset (
External soft reset (
Software watchdog reset
Bus monitor reset
Host reset command through JTAG
1.
2.
Reset Timing
Peak-to-peak.
Not tested. Guaranteed by design.
1
with CLKIN phase jitter of ±100 ps.
Input/ Output
Input/ Output
Direction
1
Internal
Internal
Internal
Input
PORESET
Characteristic
SRESET
HRESET
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0
Table 9. System Clock Parameters (continued)
)
Initiates the soft reset flow. The MSC8113 detects an external assertion of SRESET only if it occurs
Initiates the power-on reset flow that resets the MSC8113 and configures various attributes of the
MSC8113. On PORESET, the entire MSC8113 device is reset. SPLL states is reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64
bits port or a System Bus 64 bits port are configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC8113. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
most configurable features are reconfigured. These features are defined in the 32-bit hard reset
configuration word described in Hard Reset Configuration Word section of the Reset chapter in the
MSC8113 Reference Manual.
while the MSC8113 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the SC140 extended cores are reset, and system configuration is maintained.
When the MSC8113 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
When the MSC8113 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
)
)
Table 10. Reset Sources
Description
Min
800
—
—
Max
1200
1600
200
500
Freescale Semiconductor
Unit
MHz
MHz
MHz
ps
ps