MSC100ABIRM Motorola / Freescale Semiconductor, MSC100ABIRM Datasheet - Page 74

• Manufacturer Part Number: MSC100ABIRM
• Description: SC100 Application Binary Interface Reference Manual
• Manufacturer: Motorola / Freescale Semiconductor

Endian Support
5.3 Comments
The following are some comments related to some of the instructions. Based on these comments, a more
detailed definition of these cases will be described in a future version of this document.
5.3.1 MOVE Multiple Registers
In case of instructions that access more than one register (such as MOVE.2W, etc.), notice should be paid
to which register of the pair uses what address. For example, in the following instruction, d0 uses A0+A1
and d1 uses A2+A3 in little endian mode.
MOVE.2W d0:d1,(r0)
For all instructions except the VSL instructions, the relevant registers are consecutive starting at an
“aligned” number.
5.3.2 MOVE.L for the Extension Registers
MOVE.L for data extensions has also single-extension variants.
The location of this extension in memory depends on the parity of the register number.
5.3.3 PUSH/POP Instructions
PUSH/POP instructions are 32-bit operations. In case two such instructions are used, the identity of which
operand ends where in memory should be defined.
PUSH/POP can also be done on single or paired extensions—the same as MOVE.L for extension. In case
of a paired extension operand, it is not like grouping to PUSH/POP together.
5.3.4 BSR/JSR
BSR/JSR, etc. also push the SR, so the comment on PUSH instructions also apply here.
5.3.5 Control instructions
ILLEGAL and “interrupt service” will be added to the table of Control Instructions (Table 5-5).
5-18
SC100 Application Binary Interface
Preliminary (April 2000)