MSC100ABIRM Motorola / Freescale Semiconductor, MSC100ABIRM Datasheet - Page 62
MSC100ABIRM
Manufacturer Part Number
MSC100ABIRM
Description
SC100 Application Binary Interface Reference Manual
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
1.MSC100ABIRM.pdf
(86 pages)
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Endian Support
5.1.3 Instruction Word Transfers
Instruction words are transferred to the core from the memory over the Program Data Bus (PDB), to
special instruction registers in the Program Dispatch Unit.
The instruction registers can be accessed only with 128-bit width (8 instructions).
5-6
Fetch A0
Move.4W A0
Move.4W A8
Little Endian
7
I3
I7
I11
6
5
SC140
CORE
I2
I6
I10
4
3
I1
I5
I9
2
1
I0
I4
I8
0
Figure 5-5. Program Memory Organization
0
8
16 (10h)
24 (18h)
32 (20h)
64 bit XA-BUS
64 bit XB-BUS
128 bit P-BUS
Figure 5-6. Instruction Moves
Big End
I0I1I2I3
I4I5I6I7
Preliminary (April 2000)
I7I6I5I4
I3I2I1I0
Little End
I3I2I1I0
I7I6I5I4
Big Endian
0
Big Endian
Little Endian
7
0
I0
I4
I8
I0
I4
I8
I3
I7
I11
1
6
1
2
5
2
I1
I5
I9
I1
I5
I9
I2
I6
I10
SC100 Application Binary Interface
3
3
4
4
4
3
I2
I6
I10
I2
I6
I10
I1
I5
I9
5
2
5
6
1
6
I3
I7
I11
I3
I7
I11
I0
I4
I8
7
0
7
0
8
16 (10h)
24 (18h)
32 (20h)
0
8
16 (10h)
24 (18h)
32 (20h)
0
8
16 (10h)
24 (18h)
32 (20h)
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