M25PE40-VMP6TP Numonyx, B.V., M25PE40-VMP6TP Datasheet - Page 26

• Manufacturer Part Number: M25PE40-VMP6TP
• Description: 4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout
• Manufacturer: Numonyx, B.V.

Instructions
6.5
Note:
26/62
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register.
The Status Register BPi and SRWD bits are available in the M25PE40 in the T9HX process
only. See
Before the Write Status Register (WRSR) instruction can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (D).
The instruction sequence is shown in
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is t
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in
the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal (see
If a Write Status Register (WRSR) instruction is interrupted by a Reset Low pulse, the
internal cycle of the Write Status Register operation (whose duration is t
(provided that the supply voltage V
device enters the Reset mode (see also
and
Figure 11. Write Status Register (WRSR) instruction sequence
Table 24: Timings after a Reset Low
Important note on page 6
S
C
D
Q
Table
0
1
High Impedance
Section
3. The Write Status Register (WRSR) instruction also allows
2
Instruction
CC
3
for more details.
4
Figure
6.4.4).
remains within the operating range). After that the
Table 12: Device status after a Reset Low pulse
5
pulse).
6
11.
7
MSB
7
8
6
9 10 11 12 13 14 15
5
Register in
4
Status
3
2
1
0
W
) is first completed
AI02282D
W
M25PE40
) is