74LVCH16244ADL,118 NXP Semiconductors, 74LVCH16244ADL,118 Datasheet - Page 11
![IC BUFF DVR TRI-ST 16BIT 48SSOP](/photos/6/93/69380/48-ssop_sot370-1_sml.jpg)
74LVCH16244ADL,118
Manufacturer Part Number
74LVCH16244ADL,118
Description
IC BUFF DVR TRI-ST 16BIT 48SSOP
Manufacturer
NXP Semiconductors
Series
74LVCHr
Datasheet
1.74LVCH16244ADGG51.pdf
(19 pages)
Specifications of 74LVCH16244ADL,118
Package / Case
48-SSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
4
Current - Output High, Low
24mA, 24mA
Voltage - Supply
1.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LVC
Number Of Channels Per Chip
16
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 24 mA
Input Bias Current (max)
80 uA
Low Level Output Current
24 mA
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Output Current
50 mA
Output Type
3-State
Output Voltage
6.5 V
Propagation Delay Time
11 ns (Typ) @ 1.2 V or 3 ns (Typ) @ 3.3 V
Number Of Lines (input / Output)
16 / 16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVCH16244ADL-T
74LVCH16244ADL-T
935238440118
74LVCH16244ADL-T
935238440118
NXP Semiconductors
Table 9.
[1]
74LVC_LVCH16244A_9
Product data sheet
Supply voltage
1.2 V
2.7 V
3.0 V to 3.6 V
Fig 9.
The circuit performs better when R
Test data is given in
Definitions for test circuit:
R
C
R
V
Load circuit for measuring switching times
L
L
T
EXT
Test data
= Load resistance.
= Load capacitance including jig and probe capacitance.
= Termination resistance should be equal to output impedance Z
= External voltage for measuring switching times.
Input
V
V
2.7 V
2.7 V
I
CC
Table
9.
negative
L
positive
= 1 kΩ.
pulse
pulse
0 V
0 V
V
V
t
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
I
I
r
, t
All information provided in this document is subject to legal disclaimers.
G
f
90 %
10 %
V
Rev. 09 — 18 March 2010
I
t
t
r
74LVC16244A; 74LVCH16244A
f
V
V
M
M
10 %
90 %
Load
C
50 pF
50 pF
50 pF
R T
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
L
V
DUT
CC
t
t
W
W
V
O
R
500 Ω
500 Ω
500 Ω
o
L
of the pulse generator.
C L
V
V
[1]
M
M
001aae331
t
t
V
r
f
EXT
R L
R L
V
t
open
open
open
PLH
EXT
, t
PHL
t
2 × V
2 × V
2 × V
PLZ
, t
CC
CC
CC
PZL
© NXP B.V. 2010. All rights reserved.
t
GND
GND
GND
PHZ
, t
11 of 19
PZH