74LVC244APW,112 NXP Semiconductors, 74LVC244APW,112 Datasheet - Page 9

IC BUFF/DVR TRI-ST DUAL 20TSSOP

74LVC244APW,112

Manufacturer Part Number
74LVC244APW,112
Description
IC BUFF/DVR TRI-ST DUAL 20TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet

Specifications of 74LVC244APW,112

Package / Case
20-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
4
Current - Output High, Low
24mA, 24mA
Voltage - Supply
1.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LVC
Number Of Channels Per Chip
8
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 24 mA
Input Bias Current (max)
40 uA
Low Level Output Current
24 mA
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Output Current
50 mA
Output Type
3-State
Output Voltage
6.5 V
Propagation Delay Time
2.8 ns (Typ) @ 3.3 V
Number Of Lines (input / Output)
8 / 8
Logical Function
Buffer/Line Driver
Number Of Elements
2
Number Of Channels
8
Number Of Inputs
8
Number Of Outputs
8
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Package Type
TSSOP
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.2V
Quiescent Current
40uA
Technology
CMOS
Pin Count
20
Mounting
Surface Mount
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-5001
74LVC244APW
74LVC244APW,112
74LVC244APW
935210420112
NXP Semiconductors
Table 8.
74LVC_LVCH244A_6
Product data sheet
Supply voltage
V
1.2 V
2.7 V
3.0 V to 3.6 V
Fig 7.
CC
Measurement points are given in
Logic levels: V
3-state enable and disable times.
Measurement points
Input
V
V
2.7 V
2.7 V
I
CC
OL
and V
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
OH
nOE input
output
output
are typical output voltage levels that occur with the output load.
V
0.5
1.5 V
1.5 V
GND
GND
V
V
V
M
Table
OH
CC
OL
V
I
V
8.
CC
Rev. 06 — 13 August 2009
V
M
enabled
outputs
t
PLZ
t
PHZ
Output
V
0.5
1.5 V
1.5 V
M
V
X
V
V
74LVC244A; 74LVCH244A
CC
Y
disabled
outputs
t
PZL
t
V
V
V
V
PZH
X
OL
OL
OL
+ 0.1 V
+ 0.3 V
+ 0.3 V
V
M
V
M
Octal buffer/line driver; 3-state
outputs
enabled
mna362
V
V
V
V
Y
OH
OH
OH
© NXP B.V. 2009. All rights reserved.
0.1 V
0.3 V
0.3 V
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