SAB-C161O-LM Infineon Technologies, SAB-C161O-LM Datasheet - Page 60

• Manufacturer Part Number: SAB-C161O-LM
• Manufacturer: Infineon Technologies

Specifications of SAB-C161O-LM

• Packages: PG-MQFP-80
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte

Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
1)
2)
3)
Data Sheet
RW-delay and t
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
1)
A
1)
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
Symbol
t
t
t
t
53
68
55
57
t
A
+
CC -16 +
CC 9 +
SR –
SR –
t
C
+
t
min.
F
Max. CPU Clock
(100 ns at 20 MHz CPU clock without waitstates)
t
F
= 20 MHz
t
56
F
max.
30 +
5 +
–
–
t
F
t
F
1 / 2TCL = 1 to 20 MHz
min.
–
–
-16 +
TCL - 16
+
Variable CPU Clock
t
F
t
F
max.
2TCL - 20
+ 2
1)
TCL - 20
+ 2
1)
–
–
t
t
A
A
V2.0, 2001-01
+
+
t
t
F
F
C161O
C161K
Unit
ns
ns
ns
ns