TLE 8264-2E Infineon Technologies, TLE 8264-2E Datasheet
TLE 8264-2E
Specifications of TLE 8264-2E
Related parts for TLE 8264-2E
TLE 8264-2E Summary of contents
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Table of Contents 1 HERMES Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Universal System Basis Chip HERMES Rev. 1.00 1 HERMES Overview Scalable System Basis Chip Family • Six products for complete scalable application coverage • Complete compatibility (hardware and software) across the family • TLE8264-2E (3LIN), TLE8263-2E (2LIN Limp ...
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HS CAN Transceiver • Compliant to ISO 11898-2 and 11898-5 as well as SAE J2284 • CAN data transmission rate MBaud • Supplied by dedicated input • Low power mode management • Bus wake-up capability via CAN ...
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Block Diagram The simplified block diagram illustrates only the basic elements of the SBC devices. Please refer to the information for each device in the product family for more specific hardware configurations SDI ...
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Pin Configuration 3.1 Pin Assignments Figure 2 Pin Configuration Data Sheet 7 TLE8264-2E Pin Configuration Rev. 1.0, 2009-03-31 ...
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Pin Definitions and Functions Pin Symbol Function 1 RO Reset Input/Output; open drain output, integrated pull-up resistor; active low. 2 CSN SPI Chip Select Not Input; CSN is an active low input; serial communication is enabled by pulling the ...
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Pin Symbol Function 25 TxD LIN Transceiver Data input; according to ISO 9141 and LIN specification 2.1 as LIN well as SAE J2602-2. integrated pull-up resistor. 26 RxD LIN Transceiver Data Output; according to the ISO 9141 and LIN specification ...
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State Machine 4.1 Block Description SPI cmd SBC SW Flash mode Vcc1 WD trig on L.H. act/inact SPI cmd OR WD failed Detection of falling edge at reset pin (any mode) OR undervoltage reset at V CC1µC (any mode) ...
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State Machine Description The System Basis Chip (SBC) offers ten operating modes: Power On Reset, Init, Normal, Restart, Software Flash, Sleep, Stop, Fail-Safe, Software Development, and Factory Flash Mode. The modes are controlled with one test pin and via ...
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SBC Normal Mode SBC Normal Mode is used to transmit and receive CAN and LIN messages. In this mode and can be turned-on or off by SPI command. In Normal Mode the watchdog needs to be triggered. ...
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SBC Software Flash Mode SBC Software Flash Mode is similar to SBC Normal Mode regarding voltage regulators. In this mode, the Limp Home output can be set to active LOW via SPI and the communication on CAN and LIN ...
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Table 2 SBC Restart Mode Entry Reasons and Actions SBC Mode and Configuration Entering reason Mode Config n.a Init Mode n.a. config 1/3 n.a config 1 config 3 1) Normal config 4 n.a. config 1/3 n.a n.a Software Flash n.a ...
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SBC Fail-Safe Mode In SBC Fail-Safe Mode, all voltage regulators are OFF and the transceivers are in Wake-Capable Mode. The Limp Home output is active. Conditions to enter the SBC Fail-Safe Mode are: • Watchdog trigger failure in configuration ...
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General Product Characteristics 5.1 Absolute Maximum Ratings 1) Absolute Maximum Ratings = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin T j (unless otherwise specified) Pos. Parameter Voltages 5.1.1 Supply Voltage ...
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Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions ...
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Thermal Characteristics Pos. Parameter 5.3.1 Junction Ambient Junction Ambient 5.3.2 Junction to Soldering Point Thermal Prewarning and Shutdown Junction Temperatures; V 5.3.3 , Thermal Pre-warning CC1µC ON Temperature V 5.3.4 , Thermal Prewarning CC1µC Hysteresis V V 5.3.5 Thermal ...
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Current Consumption all outputs open; Without S positive current defined flowing into pin; unless otherwise specified. Pos. Parameter Normal Mode; 5.4.1 Current Consumption for Internal Logic 5.4.2 Additional current Consumption for CAN ...
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Current Consumption (cont’ 5 all outputs open; Without S positive current defined flowing into pin; unless otherwise specified. Pos. Parameter Sleep Mode 5.4.5 Current consumption, all Wake Up Sources available. 5.4.6 Quiescent Current ...
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Internal Voltage Regulator 6.1 Block Description Vs Vref Bandgap Reference Vref Charge Pump Figure 4 Functional Block Diagram The internal voltage regulators are dual low-drop voltage regulators that can supply loads up to input voltage ...
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Table 3 Internal Voltage Regulators States SBC Mode INIT Mode Normal Mode Sleep Mode Restart Mode Software Flash Mode Stop Mode Fail-Safe Mode 6.4 Application information 6.4.1 Timing Diagram Figure 5 shows the ramp up and down of the V ...
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Electrical Characteristics 5 CC1µC CC2 = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into pin; unless T j otherwise specified. Pos. ...
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External Voltage Regulator 7.1 Block Description V is activated via SPI. The external voltage regulator circuitry is designed to drive an external PNP transistor to cc3 increase output current flexibility. Four pins are used: during production. An input voltage ...
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Application Information 7.4.1 Timing information Figure 7 shows the typical timing, ramp up and ramp down of the External Voltage Regulator, in regards to the pin VextU V_OFF Vcc3 GND Figure ...
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Table 5 Bills of material for the Device Vendor C Murata SHUNT T ON semi 1 7.4.3 Calculation The maximum current where the limit starts and the bit CC3max R resistor and the Output ...
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Electrical Characteristics SBC Normal Mode; all outputs open -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into pin; unless T j otherwise specified. ...
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Timing diagram for regulator reaction time “current increase regulation reaction time” and “current decrease regulation reaction time” V CC3 I CCbase Figure 9 Regulator Reaction Time Data Sheet I CC3base,50 rlinc rldec 28 TLE8264-2E External Voltage Regulator t ...
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High Speed CAN Transceiver 8.1 Block Description V ccHSCAN CANH CANL R SPLIT SPLIT GND Figure 10 Functional Block Diagram 8.2 High-speed CAN Description The Controller Area Network (CAN) transceiver part of the SBC provides high-speed (HS) differential mode ...
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CAN Normal Mode To transfer the CAN transceiver into the CAN Normal Mode, an SPI word must be sent. This mode is designed for normal data transmission/reception within the HS CAN network. It can be accessed in Normal Mode ...
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CAN_H WAKE CAN_L PATTERN BUS WAIT BUS OFF Vdiff V cc1µ HSCAN RxD CAN Wake capable mode RO SBC Sleep mode Figure 11 Timing during Transition from Sleep to Normal Mode Wake-Up in SBC Stop Mode In SBC ...
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CAN OFF Mode CAN OFF Mode, which can be accessed in the SBC Stop, Sleep, Restart and Normal modes, and automatically accessed in SBC Init and Factory Flash modes, is used to completely stop CAN activities. In CAN OFF ...
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Failure Detection All failures are reported in the SPI diagnostic encoder, the TxD time-out is reported as TxD shorted to GND. In case of local failure and Bus Dominat Clamped failure, the transceiver is automatically switched to the CAN ...
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Failure Overtemp ON OFF TxD CAN V CC1µC GND V diff Figure 13 Release of the Transmission after Overtemperature 8.4.5 Permanent RxD Recessive Clamping If the RxD signal is permanently recessive (such as shorted to bus, the host microcontroller of ...
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... In the case the application doesn’t request the SPLIT pin feature, the pin has to be left open. CANH TLE 8264 SPLIT 10nF CANL Figure 14 Application example for the SPLIT Pin . Data Sheet 60Ohm CAN split Bus termination 60Ohm 10nF split 1,5 kOhm ...
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Electrical Characteristics V V 4.75 V < < ccHSCAN S with respect to ground; positive current flowing into pin; unless otherwise specified. Pos. Parameter CAN Bus Receiver 8.6.1 Differential Receiver ...
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Electrical Characteristics (cont’ 4.75 V < < ccHSCAN S with respect to ground; positive current flowing into pin; unless otherwise specified. Pos. Parameter CAN Bus Transmitter 8.6.10 CANH/CANL ...
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Electrical Characteristics (cont’ 4.75 V < < ccHSCAN S with respect to ground; positive current flowing into pin; unless otherwise specified. Pos. Parameter 8.6.28 TxD Input Hysteresis 8.6.29 ...
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V TxD V cc1µC GND V DIFF V RxD V cc1µC GND Figure 15 Timing Diagrams for Dynamic Characteristics Data Sheet t t d(L),T V diff, rd_N t d(L),R t d(L),TR 0 cc1µC 39 High Speed CAN Transceiver ...
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WK Pin 9.1 Block Description I WK Figure 16 Functional Block Diagram V The internal voltage regulator ( WK input pin is a bi-level sensitive input. This means that both transitions, HIGH to LOW and LOW to HIGH, result ...
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V WK Figure 17 Wake-up Timing 9.2.1 Transition from Normal to Sleep Mode. The SBC can not be sent from Normal Mode to Sleep Mode with uncleared interrupt in the WK interrupt bits “ pin” and “WK 1 ...
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Electrical Characteristics V = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into = 5 pin; unless otherwise specified. Pos. Parameter 9.3.1 WK Input Threshold ...
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LIN Transceiver The SBC includes up to three LIN blocks, but this chapter describes only one because all three LIN block are completely identical. 10.1 Block Description BUS BUSx Figure 18 Functional Block Diagram 10.2 LIN ...
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Slope Selection The LIN transceiver offers a LIN Low Slope Mode for 10.4 kBaud communication and a LIN Normal Slope Mode for 20 kBaud communication. The only difference is the behavior of the transmitter. In LIN Low Slope Mode, ...
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LIN Receive Only Mode In LIN Receive Only Mode (RxD only), the driver stage is de-activated but reception is still possible. This mode is accessible by an SPI command. 10.2.6 LIN Flash Mode In LIN Flash Mode, the slope ...
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V BUSX WAKE BUS PATTERN Idle V cc 1µ RxD LIN Wake capable mode Reset (RO) SBC Sleep mode Figure 19 Timing during Transition from SBC Sleep to SBC Normal Mode 10.3.1 Transition from SBC Normal to Sleep ...
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Failure Detection All failures are reported in the SPI Diagnostic Encoder except the TxD time-out feature, reported as TxD shorted to GND and over temperature, which is not reported. In case of failure, the transceiver is automatically switched to ...
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Failure Overtemp ON OFF TxD LIN V CC1µC GND V LIN Figure 21 Release of the Transmission after Overtemperature 10.5.5 Permanent RxD Recessive Clamping If the RxD signal is permanently recessive (for example, shorted to the bus, the host microcontroller ...
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Electrical Characteristics 500 Ω into pin; unless otherwise specified. Pos. Parameter Receiver Output RxDX Push Pull 10.6.1 HIGH level Output Voltage 10.6.2 LOW Level Output ...
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Electrical Characteristics (cont’ 500 Ω into pin; unless otherwise specified. Pos. Parameter Bus Receiver BusX 10.6.7 Receiver Threshold Voltage, recessive to dominant edge 10.6.8 Receiver ...
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Electrical Characteristics (cont’ 500 Ω into pin; unless otherwise specified. Pos. Parameter Bus Transmitter BusX 10.6.15 Bus Serial Diode Voltage Drop 10.6.16 Bus Recessive Output ...
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Electrical Characteristics (cont’ 500 Ω into pin; unless otherwise specified. Pos. Parameter Dynamic Transceiver Characteristics BusX 10.6.30 Propagation Delay, bus dominant to RxD LOW 10.6.31 ...
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Electrical Characteristics (cont’ 500 Ω into pin; unless otherwise specified. Pos. Parameter 10.6.39 Duty Cycle D3 (for worst case at 10.4 kBit/s) Low Slope Mode ...
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Supervision Functions 11.1 Reset Function 11.1.1 Description The reset output pin RO provides information to the microcontroller, for example, in the event that the output voltage has fallen below the undervoltage threshold reset signal remains LOW initially. When the ...
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Reset from Outside If the reset pin RO is pulled to low from outside while no reset low is issued by the SBC, the device goes to Restart Mode. In Restart Mode an reset is issued by the SBC, ...
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Time-out Watchdog The Time-out Watchdog is an easier and less secure type of watchdog. Compared to the Window Watchdog there is no closed window existing. The watchdog trigger can be done any time within the watchdog time. A watchdog ...
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Window Watchdog Timing (SPI CWmax t CWmin closed window Figure 23 Window Watchdog Definitions Refresh bit RO Watchdog timer reset normal operation Figure 24 Window Watchdog Timing Diagram for ...
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Inhibition of the watchdog During SBC Stop Mode and SBC SW Flash Mode possible to deactivate the watchdog. To avoid unwished deactivation of the watchdog, a special protocol has to be followed, prior deactivating the watchdog. Please ...
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Electrical Characteristics V = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current = 5 defined flowing into pin; unless otherwise specified. Pos. Parameter Reset ...
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Interrupt Function 12.1 Interrupt Description The interrupt pin has a general purpose function to point out to the microcontroller either a wake up, a failure condition or the switch voltage regulator. Figure 26 gives the hardware ...
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Table 11 Interrupt sources Interrupt sources V Undervoltage at (except during switch off CC2 V Undervoltage at (except during switch off CC3 V Over current at (except during inhibition) CC3 V Voltage at (during switch on CC2 V Voltage at ...
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Rising event (Vcc2 above limit ) is shown Vcc2 switched off by SPI Vcc2 INT pin SPI DI programming Read Only Mode Select Bits 111 Conf. Select 000 Conf. Select 001 Conf. Select 002 INT bit UV_V CC2 Figure 27 ...
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The interrupt UV_Vcc2 that is generated by an under-voltage on sensitive on rising and falling event and the interrupt bit also shows the state of the device and function. Undervoltage Falling event (Vcc2 below limit ) , rising event (Vcc2 ...
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Interrupt Timing Figure 30 illustrates the interrupt timing. The INT output is set LOW as soon as an interrupt condition occurs. The INT pin is released after a SPI interrupt buffer read out command, that is performed with a ...
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Electrical Characteristics . V = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current = 5 defined flowing into pin unless otherwise specified. Pos. Parameter ...
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Limp Home 13.1 Description The Limp Home outputs are a very useful way to control safety critical functions independent of the microcontroller, such as turning on or off critical load during a microcontroller failure. 13.2 Limp Home output The ...
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V S LH_ PL / test Figure 33 LH_PL/ Test block diagram 13.2.3 Test Pin The LH_PL/Test pin is used to set the SBC chip into SBC Software Development Mode. When the Test pin is connected to GND, the SBC ...
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Activation of the Limp Home Outputs The reason to activate the Limp Home pins and the consequences are listed in Table 12 Limp Home, Function of the SBC Mode SBC Mode Limp Home Outputs INIT Mode OFF Normal Mode ...
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Vs V SthUVx Vcc1µC V RTx GND RO SBC Sleep SBC Restart t Wake Up RDx Limp home GND V Figure 34 undervoltage time-out timing cc1µC Data Sheet V RTx t Vcc1UVTO SBC Normal SBC Restart TLE8264-2E ...
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Electrical Characteristics V = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current = 5 defined flowing into pin unless otherwise specified. Pos. Parameter Limp ...
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Configuration Select 14.1 Configuration select The Configuration select is used to set the device for two different SBC behaviors; please refer to for detailed information. Depending on the requirements of the application, the goes to Fail-Safe Mode in case ...
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Serial Peripheral Interface 15.1 SPI Description The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK supplied by the microcontroller. The output word appears synchronously at the data ...
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SPI Input Data MSB Input Data WD refresh Res. Res. Wrong Reset WD set INTERRUPT MASK LIN3 LIN3 failure failure 1 0 Cyclic /off LIN CAN 10.4k 1 ...
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SPI Output Data MSB Output Data WK state INT Res. Wrong Status or Reset WD set INTERRUPT event LIN3 LIN3 failure failure 1 0 Cyclic /off LIN CAN ...
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SBC Configuration Setting and Read Out 15.5.2.1 Mode selection bits and configuration select Table 14 lists the encoding of the possible SBC mode. Except SBC Restart and Init Mode which are most of time entered automatically, all others SBC ...
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Interrupt Register Encoder Table 16 lists all interrupts the SBC can generates. The microcontroller should read the correct register to release the INT pin. By default, all interrupt sources are enabled. The microcontroller can decide to inhibit a specific ...
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Table 16 Interrupt Register encoder (cont’d) CS Bit Name Default Value (INPUT) Configuration select 001 (SBC Failure interrupt) 001 OTP_V 1 cc1µC OT_HSCAN 1 OT_V 1 cc2 UV_V 1 cc3 SPI Fail 1 Reset 1 Wrong WD set 1 V ...
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CAN / LIN failure encoder Table 17 describes the encoding of the possible internal CAN and LIN failures. Table 17 CAN / LIN Failure Encoder CAN / LINx 1 Failure CAN / LINx 0 Failure Fault ...
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Table 18 Configuration Encoder Configuration Bit Name Select Configuration select 101 (SBC communication set up register) 101 LIN 10.4k CAN 1.0 LINx 1.0 Configuration select 110 (SBC Watchdog register) 110 Ti. Out / Win. Set ...
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Table 20 Watchdog Encoder Bit 10...6 Decimal calculation (ms) 00000 0 (n+1) × decimal value of 00001 1 setting 00010 2 ... ... 01111 15 n × 464 10000 16 10001 17 ... ... 11110 ...
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Limp Home failure encoder Table 22 describes the encoding of all possible reason to activate automatically the Limp Home output. Bits are set back to “000” when switching Limp Home off via SPI. Table 22 Limp Home Failure Diagnosis ...
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SPI Output Data 15.6.1 First SPI output data Since the SPI output data is sent when the SBC is receiving data, the output data are dependent of the previous SPI command Read Only command is used. Under ...
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Read Only command In the Mode Selection Bits a Read Only can be selected. The Read Only access clears the INT bits that are selected in the Configuration Select (some interrupt bits show a state, and can not be ...
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Electrical Characteristics V = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current = 5 defined flowing into pin; unless otherwise specified. Pos. Parameter SPI ...
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Electrical Characteristics (cont’ -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current = 5 defined flowing into pin; unless otherwise specified. Pos. Parameter ...
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Application Information Note: The following information is given only as a hint for the implementation of the device and should not be regarded as a description or warranty of a certain functionality, condition or quality of the device. VBAT ...
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Note: This is a very simplified example of an application circuit and bill of material. The function must be verified in the actual application. Table 25 Bills of material Ref. Option Vendor Value Capacitance C1 Y 68µF optional depending on ...
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Table 25 Bills of material Ref. Option Vendor Value Active components Semi MJD253 Infineon BCP52- Infineon BCR191W T3 N Infineon BCR191W T4 N Infineon BCR191W D1 N Infineon BAS 3010A D2 N Infineon BAS70 06 ...
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ZthJA Curve 60 Zth-JA(Ch4; 600) 50 Zth-JA(Ch4; 300) Zth-JA(Ch4; 100) 40 Zth-JA(Ch4; footprint 0,00001 0,0001 0,001 Figure 43 ZthJA Curve, Function of Cooling Area 600mm² cooling area Figure 44 Board Set-up Board set-up is done ...
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Hints for SBC Factory Flash Mode The mode is used during production of the module to flash the µC. The idea is that the µC is not supplied from the SBC but from an external 5V power supply. The ...
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Table 26 PIN in Factory Flash Mode Pin Level Vs typ. 4.5V 5V ± 2% Vcc1µC RO Pull-up resistor INT Pull-up resistor LH High impedance SDO High impedance CLK, SDI Pull-down resistor CSN Pull-up resistor TxDCAN, TxDLIN1, Pull-up resistor TxDLIN2, ...
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Package Outline 0. 0.65 = 11.05 2) 0.33 ±0. 12.8 -0.2 Index Marking Ejector Mark Polish Finish Exposed Diepad Dimensions Package PG-DSO-36-24, -41, -42 PG-DSO-36-38 PG-DSO-36-38 PG-DSO-36-24 1) Does not include plastic or metal protrusion ...
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Revision History Version Date Parameter 1.0 2009-01-30 1.0 2009-03-31 Data Sheet Changes First Rev. after Preliminary Data Sheet Editorial changes 93 TLE8264-2E Revision History Rev. 1.0, 2009-03-31 ...
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... Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...