74LVC541APW,112 NXP Semiconductors, 74LVC541APW,112 Datasheet - Page 4

• Manufacturer Part Number: 74LVC541APW,112
• Description: IC BUFF/DVR TRI-ST 8BIT 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC541APW,112

• Logic Type: Buffer/Line Driver, Non-Inverting
• Package / Case: 20-TSSOP
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: 74LVC
• Number Of Channels Per Chip: 8
• Polarity: Non-Inverting
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.2 V
• Maximum Operating Temperature: 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 24 mA
• Input Bias Current (max): 40 uA
• Low Level Output Current: 24 mA
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Output Type: 3-State
• Propagation Delay Time: 6.5 ns
• Number Of Lines (input / Output): 8 / 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1587-5; 74LVC541APW; 935260903112

Philips Semiconductors
2003 Nov 12
handbook, halfpage
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state)
Fig.1 Pin configuration SO20 and (T)SSOP20.
GND
OE1
A0
A1
A2
A3
A4
A5
A6
A7
10
1
2
3
4
5
6
7
8
9
541
MNA897
handbook, halfpage
15
14
13
12
20
19
18
17
16
11
V CC
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Fig.3 Logic Symbol (IEEE/IEC).
19
1
2
3
4
5
6
7
8
9
&
4
MNA898
EN
handbook, halfpage
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
18
17
16
15
14
13
12
11
Fig.2 Pin configuration DHVQFN20.
A0
A1
A2
A3
A4
A5
A6
A7
Top view
2
3
4
5
6
7
8
9
GND
OE1
10
GND
1
V CC
(1)
Y7
20
11
Product specification
MDB202
74LVC541A
19
18
17
16
15
14
13
12
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6