MAX9260 Maxim, MAX9260 Datasheet - Page 39

• Manufacturer Part Number: MAX9260
• Description: The MAX9259/MAX9260 chipset presents Maxim's gigabit multimedia serial link (GMSL) technology
• Manufacturer: Maxim

The MAX9260 checks the serial link for errors and stores
the number of detected decoding errors in the 8-bit
register (DECERR, 0x0D). If a large number of decoding
errors are detected within a short duration, the deserial-
izer loses lock and stops the error counter. The deserial-
izer then attempts to relock to the serial data. DECERR
resets upon successful video link lock, successful
readout of DECERR (through UART), or whenever auto-
error reset is enabled. The MAX9260 does not check
for decoding errors during the internal PRBS test and
DECERR is reset to 0x00.
The MAX9260 has an open-drain ERR output. This
output asserts low whenever the number of decoding
errors exceed the error threshold (ERRTHR, 0x0C) dur-
ing normal operation, or when at least one PRBS error is
detected during PRBS test. ERR reasserts high when-
ever DECERR (0x0D) resets, due to DECERR readout,
video link lock, or autoerror reset.
The default method to reset errors is to read the respec-
tive error registers in the MAX9260 (0x0D, 0x0E). Auto-
error reset clears the decoding-error counter (DECERR)
and the ERR output ~1Fs after ERR goes low. Autoerror
reset is disabled on power-up. Enable autoerror reset
through AUTORST (0x06 D6). Autoerror reset does not
run when the device is in PRBS test mode.
The MAX9259/MAX9260 link includes a PRBS pat-
tern generator and bit-error verification function. Set
PRBSEN = 1 (0x04 D5) first in the MAX9259 and then
the MAX9260 to start the PRBS test. Set PRBSEN = 0
(0x04 D5) first in the MAX9260 and then the MAX9259
to exit the PRBS self test. The MAX9260 uses an 8-bit
register (0x0E) to count the number of detected errors.
The control link also controls the start and stop of the
error counting. During PRBS mode, the device does not
count decoding errors and the ERR output reflects PRBS
errors only. Autoerror reset does not run when the device
is in PRBS mode.
Usually the FC is either on the serializer (MAX9259)
side for video-display applications, or on the deserial-
izer (MAX9260) side for image-sensing applications. For
the former case, both the CDS pins of the MAX9259/
Gigabit Multimedia Serial Link with Spread
of the GMSL Link (Dual µC Control)
Spectrum and Full-Duplex Control Channel
Applications Information
Microcontrollers on Both Sides
______________________________________________________________________________________
MAX9260 Error Checking
Autoerror Reset
Self PRBS Test
ERR Output
MAX9260 are set to low, and for the later case, the
CDS pins are set to high. However, if the CDS pin of the
MAX9259 is low and the CDS pin of the MAX9260 is high,
then the MAX9259/MAX9260 can both connect to FCs
simultaneously. In such a case, the FCs on either side
can communicate with the MAX9259/MAX9260 UART
protocol.
Contentions of the control link may happen if the FCs
on both sides are using the link at the same time. The
MAX9259/MAX9260 do not provide the solution for
contention avoidance. The serializer/deserealizer do not
send an acknowledge frame when communication fails
due to contention. Users can always implement a higher-
layer protocol to avoid the contention. In addition, if UART
communication across the serial link is not required, the
FCs can disable the forward and reverse control channel
through the FWDCCEN and REVCCEN bits (0x04 D[1:0])
in the MAX9259/MAX9260. UART communication across
the serial link is stopped and contention between FCs no
longer occurs. During the dual FC operation, if one of the
CDS pins on either side changes state, the link resumes
the corresponding state described in the Link Startup
Procedure section.
As an example of dual FC use in an image-sensing link,
the MAX9259 may be in sleep mode and waiting to be
waked up by the MAX9260. After wake-up, the serializer-
side FC sets the MAX9259 CDS pin low and assumes
master control of the MAX9259 registers.
In some applications, the parallel bus input clock to the
MAX9259 (PCLKIN) includes noise, which reduces link
reliability. The MAX9259 has a narrow-band jitter-filtering
PLL to attenuate frequency components outside the
PLL’s bandwidth (< 100kHz typ). Enable the jitter-filtering
PLL by setting DISFPLL = 0 (0x05 D6).
Both the video data rate (f
rate (f
applications with multiple clock speeds. Slow speed/
performance modes allow significant power savings
when a system’s full capabilities are not required. Enable
the MAX9259/MAX9260 link after PCLK_ stabilizes.
Stop PCLKIN for 5µs and restart the serial link or toggle
SEREN after each change in the parallel clock frequency
to recalibrate any automatic settings if a clean frequency
change cannot be guaranteed. The reverse control
channel remains unavailable for 350Fs after serial link
start or stop. Limit on-the-fly changes in f
tors of less than 3.5 at a time to ensure that the device
UART
) can be changed on-the-fly to support
Changing the Data Frequency
PCLK_
Jitter-Filtering PLL
) and the control data
UART
to fac-
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