MAX9260 Maxim, MAX9260 Datasheet - Page 14

• Manufacturer Part Number: MAX9260
• Description: The MAX9259/MAX9260 chipset presents Maxim's gigabit multimedia serial link (GMSL) technology
• Manufacturer: Maxim

Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
14
21, 31, 50, 60
26–29, 32–40,
42–49, 52–59
_____________________________________________________________________________________
30, 51
PIN
18
19
20
22
23
24
25
41
61
62
—
DOUT28/MCLK
PCLKOUT
DOUT27,
DOUT0–
TX/SCL
IOGND
IOVDD
NAME
PWDN
LOCK
SSEN
ERR
SCK
DRS
WS
SD
EP
Transmit/Serial Clock. UART transmit or I
pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In
I
Power-Down. Active-low power-down input requires external pulldown or pullup resis-
tors.
Error. Active-low open-drain video data error output with internal pullup to IOVDD.
ERR goes low when the number of decoding errors during normal operation exceed a
programmed error threshold or when at least one PRBS error is detected during PRBS
test. ERR is high impendence when PWDN = low.
Input/Output Ground
Open-Drain Lock Output with Internal Pullup to IOVDD. LOCK = high indicates PLLs
are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs
are not locked or incorrect serial-word-boundary alignment. LOCK remains low when
the configuration link is active. LOCK is high impedance when PWDN = low.
Word Select. I
Serial Clock. I
Serial Data. I
latched on the selected edge of PCLKOUT.
Data Output[0:28]. Parallel data outputs. Output data can be strobed on the selected
edge of PCLKOUT. Set BWS = low (24-bit mode) to use DOUT0–DOUT20 (RGB and
SYNC). DOUT21–DOUT28 are not used in 24-bit mode and are set to low. Set BWS =
high (32-bit mode) to use DOUT0–DOUT28 (RGB, SYNC, and two extra outputs).
DOUT28 can be used to output MCLK (see the Additional MCLK Output for Audio
Applications section).
1.8V to 3.3V Logic I/O Power Supply. Bypass IOVDD to IOGND with 0.1FF and 0.001FF
capacitors as close as possible to the device with the smaller value capacitor closest
to IOVDD.
Parallel Clock Output. Used for DOUT0–DOUT28.
Spread-Spectrum Enable. Parallel output spread-spectrum enable input requires
external pulldown or pullup resistors. The state of SSEN latches upon power-up or
when resuming from power-down mode (PWDN = low). Set SSEN = high for Q2%
spread spectrum on the parallel outputs. Set SSEN = low to use the parallel outputs
without spread spectrum.
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit
mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data
rates of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
Exposed Pad. EP internally connected to AGND. MUST externally connect EP to the
AGND plane to maximize thermal and electrical performance.
2
C mode, TX/SCL is the SCL output of the MAX9260’s I
2
2
S serial-data output. Disable I
2
S serial-clock output
S word-select output.
MAX9260 Pin Description (continued)
FUNCTION
2
C serial-clock output with internal 30kI
2
S to use SD as an additional data output
2
C master.