SAA7146AH/V4,557 NXP Semiconductors, SAA7146AH/V4,557 Datasheet - Page 76
SAA7146AH/V4,557
Manufacturer Part Number
SAA7146AH/V4,557
Description
IC VIDEO SPCI BRIDGE HP 160-QFP
Manufacturer
NXP Semiconductors
Type
Video Bridger
Datasheet
1.SAA7146AHV4557.pdf
(139 pages)
Specifications of SAA7146AH/V4,557
Package / Case
160-QFP
Applications
DTV
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1318
935269343557
SAA7146AHBB
935269343557
SAA7146AHBB
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAA7146AH/V4,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Philips Semiconductors
Table 62 YUV 4 : 2 : 2 format
Table 63 YUV 4 : 1 : 1 format
The following formats are planar YUV formats and use the three video FIFOs and three video DMA Channels 1, 2 and 3.
The byte phase of the first sample each line is defined by the 2 LSBs of every DMA base.
7.11.1.3
There are two pseudo CLUT formats, which derives its bits from RGB-24 or YUV-24 by truncation, or by error diffusion
dither. The byte phase of the first sample each field is defined by 2 LSBs of DMA base.
All 8-bit formats are packed formats, 4 samples go into one Dword. The byte phase of the first sample of each line is
defined by the 2 LSBs of the DMA base. All except 8 use FIFO 1.
Table 64 8-bit formats
2004 Aug 25
Y
1
2
3
pixel
1
YUV 4 : 4 : 4; U and V sampled with every Y sample
YUV 4 : 2 : 2; U and V sampled co-sided with first Y sample (of 2 samples in-line)
YUV 4 : 2 : 0; MPEG U and V sampled at upper left sample of 4 sample in square (2
YUV-9 video; U and V sampled at selected sample of 16 samples in-square (4
YUV1; YUYV, YUYV...
YUV2; YYUU, YYVV...
Y8G; Only Y or inverted Y
RGB-8 (3 : 3 : 2); Red has 3 bits, Green has 3 bits, Blue has 2 bits
YUV8 (4 : 2 : 2); Y has 4 bits, U has 2 bits, V has 2 bits. Y = 0 doesn’t exist, to handle 16-bit colour formats for pseudo
CLUT. After dithering, Y
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
8; 8-bit alpha information, to be master-read through FIFO 2 and merged into RGB-24 with alpha.
BUS CYCLE
3
BIT 31 TO BIT 24
BIT 31 TO BIT 24
8-bit formats
Y
Y
Y
1
3
7
min
BIT 31 TO BIT 24
= 1.
V
pixel
0
2
BIT 23 TO BIT 16
BIT 23 TO BIT 16
PACKING WITHIN 32-BIT Dword
PACKING WITHIN 32-BIT Dword
V
V
V
0
4
6
BIT 23 TO BIT 16
PACKING WITHIN 32-BIT Dword
76
Y
pixel
0
1
BIT 15 TO BIT 8
BIT 15 TO BIT 8
Y
Y
Y
0
2
5
BIT 15 TO BIT 8
4)
2)
U
pixel
0
0
U
U
Y
BIT 7 TO BIT 0
BIT 7 TO BIT 0
4
0
4
Product specification
BIT 7 TO BIT 0
SAA7146A
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