SAA7146AH/V4,557 NXP Semiconductors, SAA7146AH/V4,557 Datasheet - Page 116
SAA7146AH/V4,557
Manufacturer Part Number
SAA7146AH/V4,557
Description
IC VIDEO SPCI BRIDGE HP 160-QFP
Manufacturer
NXP Semiconductors
Type
Video Bridger
Datasheet
1.SAA7146AHV4557.pdf
(139 pages)
Specifications of SAA7146AH/V4,557
Package / Case
160-QFP
Applications
DTV
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1318
935269343557
SAA7146AHBB
935269343557
SAA7146AHBB
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAA7146AH/V4,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Philips Semiconductors
7.17
7.17.1
The I
data exchange. Only two bus lines are required: a serial
clock line (SCL) and a serial data line (SDA). It’s a true
multi-master bus including collision detection and
arbitration to prevent data corruption if two or more
masters simultaneously initiate data transfers. Serial clock
synchronization allows devices with different bit rates to
communicate via the same serial bus. The block diagram
is shown in Fig.41.
7.17.2
The I
generation and bus control arbitration are controlled by
hardware. The status register (IICSTA) reflects the status
of the interface and the I
2004 Aug 25
handbook, full pagewidth
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
2
2
C-bus is a simple 2-wire bus for efficient inter-IC
C-bus performs byte oriented data transfers. Clock
I
2
C-bus interface
G
F
UNCTIONAL DESCRIPTION
ENERAL DESCRIPTION
SDA
SCL
2
C-bus (see Table 110).
ARBITRATION AND SYNC LOGIC
Fig.41 Block diagram of I
BUS CLOCK GENERATOR
8-BIT SHIFT REGISTER
116
2
An interrupt after execution may be enabled optionally.
The bus clock generator supports clock rates from
5 to 400 kHz.
The I
control register (IICTRF) which is shown in Table 112.
A write to this register starts the transfer sequence where
up to 3 bytes are transferred: BYTE2, BYTE1 and BYTE0.
Any of these 3 bytes may be disabled or enabled for use
(as data byte or 7-bit address plus RW bit) in three I
protocol functions:
All bus operations are done via these three functions.
The functional usage of each single byte is defined by the
byte specific attribute information (see Table 113).
CONTROL
C-bus serial interface.
START: start/restart and address device
CONT: transfer data and continue
STOP: transfer data and stop.
2
STATUS REGISTER (IICSTA)
C-bus interface is programmed through the transfer
TRANSFER ATTRIBUTES
BYTE 0
BYTE 1
BYTE 2
MGG278
Product specification
SAA7146A
2
C-bus
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