ISL98001CQZ-210 Intersil, ISL98001CQZ-210 Datasheet - Page 18

• Manufacturer Part Number: ISL98001CQZ-210
• Description: IC TRPL VIDEO DIGITIZER 128-MQFP
• Manufacturer: Intersil
• Type: Video Digitizerr

Specifications of ISL98001CQZ-210

• Applications: Digital TV, Displays, Digital KVM, Graphics Processing
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Listing
Technical Highlights
The ISL98001 provides all the features of traditional triple
channel video AFEs, but adds several next-generation
enhancements, bringing performance and ease of use to
new levels.
DPLL
All video AFEs must phase lock to an HSYNC signal,
supplied either directly or embedded in the video stream
(Sync On Green). Historically this has been implemented as
a traditional analog PLL. At SXGA and lower resolutions, an
analog PLL solution has proven adequate, if somewhat
troublesome (due to the need to adjust charge pump
currents, VCO ranges and other parameters to find the
optimum trade-off for a wide range of pixel rates).
As display resolutions and refresh rates have increased,
however, the pixel period has shrunk. An XGA pixel at a
60Hz refresh rate has 15.4ns to change and settle to its new
value. But at UXGA 75Hz, the pixel period is 4.9ns. Most
consumer graphics cards (even the ones with “350MHz”
0x25
0x2B
ADDRESS
Sync Separator Control (0x00)
Crystal Multiplier (0x14)
REGISTER (DEFAULT VALUE)
(Continued)
18
BIT(S)
7:0
0
1
2
3
4
5
6
7
ISL98001
Three-state Sync
Outputs
COAST Polarity
HS
Reserved
VSYNC
Reserved
Reserved
VS
Crystal Multiplier
FUNCTION NAME
OUT
OUT
OUT
Mode
Lock Edge
DACs) spend most of that time slewing to the new pixel
value. The pixel may settle to its final value with 1ns or less
before it begins slewing to the next pixel. In many cases it
rings and never settles at all. So precision, low-jitter
sampling is a fundamental requirement at these speeds, and
a difficult one for an analog PLL to meet.
The ISL98001's DPLL has less than 250ps of jitter, peak to
peak, and independent of the pixel rate. The DPLL generates
64-phase steps per pixel (vs the industry standard 32), for
fine, accurate positioning of the sampling point. The crystal-
locked NCO inside the DPLL completely eliminates drift due to
charge pump leakage, so there is inherently no frequency or
phase change across a line. An intelligent all-digital loop
filter/controller eliminates the need for the user to have to
program or change anything (except for the number of pixels)
to lock over a range from interlaced video (10MHz or higher)
to UXGA 60Hz (170MHz, with the ISL98001-170).
The DPLL eliminates much of the performance limitations and
complexity associated with noise-free digitization of high
speed signals.
Mode
0: VSYNC
active (default).
1: VSYNC
three-state.
0: Coast active high (default)
1: Coast active low
Set to 0 for internal VSYNC extracted from CSYNC.
Set to 0 or 1 as appropriate to match external VSYNC
or external COAST.
0: HS
HSYNC
backward in time as HS
(X980xx default).
1: HS
HSYNC
time as HS
Set to 0
0: VSYNC
providing “perfect” VSYNC signal (default).
1: VSYNC
Set to 0
Set to 0
0: VS
1: COAST (including pre- and post-coast COAST) is
output on VS
When using the ISL98001-275, the value in this
register must need to be changed to achieve the
maximum conversion rate (see “Initialization” on
page 26. This register may also be adjusted to lower
power consumption at slower pixel rates (see the
“Reducing Power Dissipation” on page 26 for more
information).
OUT
OUT
OUT
IN
IN
's trailing edge is locked to selected
's lock edge. Leading edge moves
's leading edge is locked to selected
's lock edge. Trailing edge moves forward in
OUT
OUT
OUT
OUT
is output on VS
OUT
OUT
, HSYNC
, HSYNC
is aligned to HSYNC
is “raw” integrator output.
width is increased.
pin.
DESCRIPTION
OUT
OUT
OUT
OUT
, VS
, VS
width is increased
pin (default).
OUT
OUT
OUT
, HS
, HS
September 21, 2010
OUT
OUT
edge,
are
are in
FN6148.5